Renesas SH7781 用户手册
20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 982 of 1658
REJ09B0261-0100
REJ09B0261-0100
20.3.4
GA Interrupt Source Indication Clear Register (GACICR)
GACICR is in the GDTA common register block and clears interrupt source indication for each
module. Bits in this register are read as 0.
module. Bits in this register are read as 0.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
BIt:
Initial value:
R/W:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CL_
ENCR
MC_
ENCR
CL_
ERCR
MC_
ERCR
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
W
W
W
W
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
BIt:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
31 to 4
⎯ All
0
⎯ Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
3
MC_ERCR
0
W
Clears indication of an MC error interrupt (clears the
MC_ERR bit)
MC_ERR bit)
0: No effect
1: Clears error interrupt indication
2
CL_ERCR
0
W
Clears indication of a CL error interrupt (clears the
CL_ERR bit)
CL_ERR bit)
0: No effect
1: Clears error interrupt indication
1
MC_ENCR
0
W
Clears indication of an MC processing end interrupt
(clears the MC_END bit)
(clears the MC_END bit)
0: No effect
1: Clears processing end interrupt indication
0
CL_ENCR
0
W
Clears indication of a CL processing end interrupt (clears
the CL_END bit)
the CL_END bit)
0: No effect
1: Clears processing end interrupt indication