Renesas SH7781 用户手册
20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 983 of 1658
REJ09B0261-0100
20.3.5
GA Interrupt Enable Register (GACIER)
GACIER is in the GDTA common register block and sets interrupt output for each module.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
BIt:
Initial value:
R/W:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CL_
ENEN
MC_
ENEN
CL_
EREN
MC_
EREN
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
BIt:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
31 to 4
⎯ All
0
⎯ Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
3
MC_EREN
0
R/W
Controls output of an MC module error interrupt
0: Does not output the interrupt.
1: Outputs the interrupt.
2
CL_EREN
0
R/W
Controls output of a CL module error interrupt
0: Does not output the interrupt.
1: Outputs the interrupt.
1
MC_ENEN
0
R/W
Controls output of an MC module processing end
interrupt
interrupt
0: Does not output the interrupt.
1: Outputs the interrupt.
0 CL_ENEN
0 R/W
Controls
output
of
a CL module processing end interrupt
0: Does not output the interrupt.
1: Outputs the interrupt.