Renesas SH7781 用户手册
7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 154 of 1658
REJ09B0261-0100
REJ09B0261-0100
Bit Bit
Name
Initial
Value
Value
R/W Description
31 to 10 VPN
Undefined R/W
Virtual Page Number
9, 8
⎯ All
0
R
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
description in General Precautions on Handling of
Product.
7 to 0
ASID
Undefined R/W
Address Space Identifier
7.2.2
Page Table Entry Low Register (PTEL)
PTEL is used to hold the physical page number and page management information to be recorded
in the UTLB by means of the LDTLB instruction. The contents of this register are not changed
unless a software directive is issued.
in the UTLB by means of the LDTLB instruction. The contents of this register are not changed
unless a software directive is issued.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Bit:
0
0
0
0
Initial value:
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PPN
PPN
V
SZ1
PR1
PR0
SZ0
C
D
SH
WT
R/W
R/W
R/W
R/W
R/W
R/W:
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
31 to 29
⎯ All
0
R
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
description in General Precautions on Handling of
Product.
28 to 10 PPN
Undefined R/W
Physical Page Number
9
⎯ 0 R
Reserved
For details on reading from or writing to this bit, see
description in General Precautions on Handling of
Product.
description in General Precautions on Handling of
Product.