Renesas SH7781 用户手册
7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 155 of 1658
REJ09B0261-0100
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
8 V
Undefined
R/W
7 SZ1 Undefined
R/W
6 PR1 Undefined
R/W
5 PR0 Undefined
R/W
4 SZ0 Undefined
R/W
3 C
Undefined
R/W
2 D
Undefined
R/W
1 SH Undefined
R/W
Page Management Information
The meaning of each bit is same as that of
corresponding bit in Common TLB (UTLB).
corresponding bit in Common TLB (UTLB).
For details, see section 7.3, TLB Functions (TLB
Compatible Mode; MMUCR.ME = 0) and section 7.4,
TLB Functions (TLB Extended Mode; MMUCR.ME = 1).
Compatible Mode; MMUCR.ME = 0) and section 7.4,
TLB Functions (TLB Extended Mode; MMUCR.ME = 1).
Note:
SZ1, PR1, SZ0, and PR0 bits are valid only in
TLB compatible mode.
TLB compatible mode.
0 WT Undefined
R/W
7.2.3
Translation Table Base Register (TTB)
TTB is used to store the base address of the currently used page table, and so on. The contents of
TTB are not changed unless a software directive is issued. This register can be used freely by
software.
TTB are not changed unless a software directive is issued. This register can be used freely by
software.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Bit:
Initial value:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TTB
TTB
R/W
R/W
R/W
R/W
R/W
R/W:
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W