Motorola MCF5281 用户手册
4-8
MCF5282 User’s Manual
MOTOROLA
Cache Programming Model
31
30
29
28
27
26
25
24
23
22
21
20
19
16
Field CENB
—
CPD CFRZ
—
CINV DIDI
DISD INVI INVD
—
Reset
0000_0000_0000_0000
R/W
W
15
11
10
9
8
7
6
5
4
3
2
1
0
Field
—
CEIB DCM DBWE
—
DWP EUSP
—
CLNF
Reset
0000_0000_0000_0000
R/W
W
Figure 4-2. Cache Control Register (CACR)
Table 4-4. CACR Field Descriptions
Bits
Name
Description
31
CENB
Cache enable.
The memory array of the cache is enabled only if CENB is asserted. This bit, along with
the DISI (disable instruction caching) and DISD (disable data caching) bits, control the cache
configuration.
0 Cache disabled
1 Cache enabled
Table 4-5 describes cache configuration.
configuration.
0 Cache disabled
1 Cache enabled
Table 4-5 describes cache configuration.
30–29
—
Reserved, should be cleared.
28
CPDI
Disable CPUSHL invalidation. When the privileged CPUSHL instruction is executed, the cache entry
defined by bits [10:4] of the address is invalidated if CPDI = 0. If CPDI = 1, no operation is performed.
0 Enable invalidation
1 Disable invalidation
defined by bits [10:4] of the address is invalidated if CPDI = 0. If CPDI = 1, no operation is performed.
0 Enable invalidation
1 Disable invalidation
27
CFRZ
Cache freeze. This field allows the user to freeze the contents of the cache. When CFRZ is asserted line
fetches can be initiated and loaded into the line-fill buffer, but a valid cache entry can not be overwritten.
If a given cache location is invalid, the contents of the line-fill buffer can be written into the memory
array while CFRZ is asserted.
0 Normal Operation
1 Freeze valid cache lines
fetches can be initiated and loaded into the line-fill buffer, but a valid cache entry can not be overwritten.
If a given cache location is invalid, the contents of the line-fill buffer can be written into the memory
array while CFRZ is asserted.
0 Normal Operation
1 Freeze valid cache lines
26–25
—
Reserved, should be cleared.
24
CINV
Cache invalidate. The cache invalidate operation is not a function of the CENB state (that is, this
operation is independent of the cache being enabled or disabled). Setting this bit forces the cache to
invalidate all, half, or none of the tag array entries depending on the state of the DISI, DISD, INVI, and
INVD bits. The invalidation process requires several cycles of overhead plus 128 machine cycles to
clear all tag array entries and 64 cycles to clear half of the tag array entries, with a single cache entry
cleared per machine cycle. The state of this bit is always read as a zero. After a hardware reset, the cache
must be invalidated before it is enabled.
0 No operation
1 Invalidate all cache locations
Table 4-6 describes how to set the cache invalidate all bit.
operation is independent of the cache being enabled or disabled). Setting this bit forces the cache to
invalidate all, half, or none of the tag array entries depending on the state of the DISI, DISD, INVI, and
INVD bits. The invalidation process requires several cycles of overhead plus 128 machine cycles to
clear all tag array entries and 64 cycles to clear half of the tag array entries, with a single cache entry
cleared per machine cycle. The state of this bit is always read as a zero. After a hardware reset, the cache
must be invalidated before it is enabled.
0 No operation
1 Invalidate all cache locations
Table 4-6 describes how to set the cache invalidate all bit.
23
DISI
Disable instruction caching. When set, this bit disables instruction caching. This bit, along with the
CENB (cache enable) and DISD (disable data caching) bits, control the cache configuration. See the
CENB definition for a detailed description.
0 Do not disable instruction caching
1 Disable instruction caching
Table 4-5 describes cache configuration and Table 4-6 describes how to set the cache invalidate all bit.
CENB (cache enable) and DISD (disable data caching) bits, control the cache configuration. See the
CENB definition for a detailed description.
0 Do not disable instruction caching
1 Disable instruction caching
Table 4-5 describes cache configuration and Table 4-6 describes how to set the cache invalidate all bit.