Motorola MCF5281 用户手册
MOTOROLA
Chapter 4. Cache
4-9
Cache Programming Model
22
DISD
Disable data caching. When set, this bit disables data caching. This bit, along with the CENB (cache
enable) and DISI (disable instruction caching) bits, control the cache configuration. See the CENB
definition for a detailed description.
0 Do not disable data caching
1 Disable data caching
Table 4-5 describes cache configuration and Table 4-6 describes how to set the cache invalidate all bit.
enable) and DISI (disable instruction caching) bits, control the cache configuration. See the CENB
definition for a detailed description.
0 Do not disable data caching
1 Disable data caching
Table 4-5 describes cache configuration and Table 4-6 describes how to set the cache invalidate all bit.
21
INVI
CINV instruction cache only. This bit can not be set unless the cache configuration is split (both DISI
and DISD cleared). For instruction or data cache configurations this bit is a don’t-care. For the split
cache configuration, this bit is part of the control for the invalidate all operation. See the CINV
definition for a detailed description
Table 4-6 describes how to set the cache invalidate all bit.
and DISD cleared). For instruction or data cache configurations this bit is a don’t-care. For the split
cache configuration, this bit is part of the control for the invalidate all operation. See the CINV
definition for a detailed description
Table 4-6 describes how to set the cache invalidate all bit.
20
INVD
CINV data cache only. This bit can not be set unless the cache configuration is split (both DISI and
DISD cleared). For instruction or data cache configurations this bit is a don’t-care. For the split cache
configuration, this bit is part of the control for the invalidate all operation. See the CINV definition for
a detailed description
Table 4-6 describes how to set the cache invalidate all bit.
DISD cleared). For instruction or data cache configurations this bit is a don’t-care. For the split cache
configuration, this bit is part of the control for the invalidate all operation. See the CINV definition for
a detailed description
Table 4-6 describes how to set the cache invalidate all bit.
19–11
—
Reserved, should be cleared.
10
CEIB
Cache enable noncacheable instruction bursting. Setting this bit enables the line-fill buffer to be loaded
with burst transfers under control of CLNF[1:0] for noncacheable accesses. Noncacheable accesses are
never written into the memory array.
0 Disable burst fetches on noncacheable accesses
1 Enable burst fetches on noncacheable accesses
with burst transfers under control of CLNF[1:0] for noncacheable accesses. Noncacheable accesses are
never written into the memory array.
0 Disable burst fetches on noncacheable accesses
1 Enable burst fetches on noncacheable accesses
9
DCM
Default cache mode. This bit defines the default cache mode: 0 is cacheable, 1 is noncacheable. For
more information on the selection of the effective memory attributes, see Section 4.3.2, “Memory
Reference Attributes.
0 Caching enabled
1 Caching disabled
more information on the selection of the effective memory attributes, see Section 4.3.2, “Memory
Reference Attributes.
0 Caching enabled
1 Caching disabled
8
DBWE
Default buffered write enable. This bit defines the default value for enabling buffered writes. If DBWE
= 0, the termination of an operand write cycle on the processor's local bus is delayed until the external
bus cycle is completed. If DBWE = 1, the write cycle on the local bus is terminated immediately and
the operation buffered in the bus controller. In this mode, operand write cycles are effectively decoupled
between the processor's local bus and the external bus. Generally, enabled buffered writes provide
higher system performance but recovery from access errors can be more difficult. For the ColdFire CPU,
reporting access errors on operand writes is always imprecise and enabling buffered writes further
decouples the write instruction and the signaling of the fault
0 Disable buffered writes
1 Enable buffered writes
= 0, the termination of an operand write cycle on the processor's local bus is delayed until the external
bus cycle is completed. If DBWE = 1, the write cycle on the local bus is terminated immediately and
the operation buffered in the bus controller. In this mode, operand write cycles are effectively decoupled
between the processor's local bus and the external bus. Generally, enabled buffered writes provide
higher system performance but recovery from access errors can be more difficult. For the ColdFire CPU,
reporting access errors on operand writes is always imprecise and enabling buffered writes further
decouples the write instruction and the signaling of the fault
0 Disable buffered writes
1 Enable buffered writes
7–6
—
Reserved, should be cleared.
5
DWP
Default write protection
0 Read and write accesses permitted
1 Only read accesses permitted
0 Read and write accesses permitted
1 Only read accesses permitted
4
EUSP
Enable user stack pointer. See Section 2.2.3.2, “Supervisor/User Stack Pointers (A7 and OTHER_A7)"
for more information on the dual stack pointer implementation.
0 Disable the processor’s use of the User Stack Pointer
1 Enable the processor’s use of the User Stack Pointer
for more information on the dual stack pointer implementation.
0 Disable the processor’s use of the User Stack Pointer
1 Enable the processor’s use of the User Stack Pointer
Table 4-4. CACR Field Descriptions (continued)
Bits
Name
Description