Motorola MCF5281 用户手册
6-6
MCF5282 User’s Manual
MOTOROLA
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• The FLASHBAR valid bit is programmed according to the chip mode selected at
reset (see Chapter 30, “Chip Configuration Module (CCM)” for more details). All
other bits are unaffected.
other bits are unaffected.
The FLASHBAR register contains several control fields. These fields are shown in
Figure 6-3
Figure 6-3
NOTE
The default value of the FLASHBAR is determined by the chip
configuration selected at reset (see Chapter 30, “Chip
Configuration Module (CCM)” for more information). If
external boot mode is used, then the FLASHBAR located in the
processor’s CPU space will be invalid and it must be initialized
with the valid bit set before the CPU (or modules) can access
the on-chip Flash.
configuration selected at reset (see Chapter 30, “Chip
Configuration Module (CCM)” for more information). If
external boot mode is used, then the FLASHBAR located in the
processor’s CPU space will be invalid and it must be initialized
with the valid bit set before the CPU (or modules) can access
the on-chip Flash.
NOTE
Flash accesses (reads/writes) by a bus master other than the
core, (DMA controller or Fast Ethernet Controller), or writes to
Flash by the core during programming must use the backdoor
Flash address of IPSBAR plus an offset of 0x0400_0000. For
example, for a DMA transfer from the first location of Flash
when IPSBAR is still at its default location of 0x4000_0000,
the source register would be loaded with 0x4400_0000.
Backdoor access to Flash for reads can be made by the bus
master, but it takes 2 cycles longer than a direct read of the
Flash if using its FLASHBAR address.
core, (DMA controller or Fast Ethernet Controller), or writes to
Flash by the core during programming must use the backdoor
Flash address of IPSBAR plus an offset of 0x0400_0000. For
example, for a DMA transfer from the first location of Flash
when IPSBAR is still at its default location of 0x4000_0000,
the source register would be loaded with 0x4400_0000.
Backdoor access to Flash for reads can be made by the bus
master, but it takes 2 cycles longer than a direct read of the
Flash if using its FLASHBAR address.
NOTE
The Flash is marked as valid on reset based on the RCON (reset
configuration) pin state. Flash space is valid on reset when
booting in single chip mode (RCON pin asserted and
D[26]/D[17]/D[16] set to 110), or when booting internally in
master mode (RCON asserted and D[26]/D[17]/D[16] are set
to 111 and D[18] and D[19] are set to 00). See Chapter 30,
“Chip Configuration Module (CCM)” for more details. When
the default reset configuration is not overriden, the MCF5282
will (by default) boot up in single chip mode and the Flash
space will be marked as valid at address 0x0. The Flash
configuration field is checked during the reset sequence to see
if the Flash is secured. If it is the part will always boot from
internal Flash, since it will be marked as valid, regardless of
what is done for chip configuration.
configuration) pin state. Flash space is valid on reset when
booting in single chip mode (RCON pin asserted and
D[26]/D[17]/D[16] set to 110), or when booting internally in
master mode (RCON asserted and D[26]/D[17]/D[16] are set
to 111 and D[18] and D[19] are set to 00). See Chapter 30,
“Chip Configuration Module (CCM)” for more details. When
the default reset configuration is not overriden, the MCF5282
will (by default) boot up in single chip mode and the Flash
space will be marked as valid at address 0x0. The Flash
configuration field is checked during the reset sequence to see
if the Flash is secured. If it is the part will always boot from
internal Flash, since it will be marked as valid, regardless of
what is done for chip configuration.