Motorola MCF5281 用户手册

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页码 816
7-14
MCF5282 User’s Manual
MOTOROLA
 
Functional Description  
• Self-wake mechanism. If the SELF-WAKE bit in the MCR is set at the time the 
FlexCAN enters stop mode, then upon detection of recessive to dominant transition 
on the CAN bus, the FlexCAN resets the STOP bit in the MCR and resumes its 
clocks.
Recommendations for, and features of, FlexCAN’s stop mode operation are as follows:
• Upon stop/self-wake mode entry, the FlexCAN tries to receive the frame that caused 
it to wake; that is, it assumes that the dominant bit detected is a start-of-frame bit. It 
does not arbitrate for the CAN bus then.
• Before asserting stop Mode, the CPU should disable all interrupts in the FlexCAN, 
otherwise it may be interrupted while in stop mode upon a non-wake-up condition. 
If desired, the WAKE-MASK bit should be set to enable the WAKE-INT.
• If stop mode is asserted while the FlexCAN is BUSOFF (see error and status 
register), then the FlexCAN enters stop mode and stops counting the 
synchronization sequence; it continues this count once stop mode is exited.
• The correct flow to enter stop mode with SELF-WAKE:
— assert SELF-WAKE at the same time as STOP.
— wait for STOP_ACK bit to be set.
• The correct flow to negate STOP with SELF-WAKE:
— negate SELF-WAKE at the same time as STOP.
— wait for STOP_ACK negation.
• SELF-WAKE should be set only when the MCR[STOP] bit is negated and the 
FlexCAN is ready; that is, the NOT_RDY bit in the MCR is negated.
• If STOP and SELF_WAKE are set and if a recessive to dominant edge immediately 
follows on the CAN bus, the STOP_ACK bit in the MCR may never be set, and the 
STOP bit in the MCR is reset.
• If the user does not want to have old frames sent when the FlexCAN is awakened 
(STOP with Self-Wake), the user should disable all Tx sources, including 
remote-response, before stop mode entry.
• If halt mode is active at the time the STOP bit is set, then the FlexCAN assumes that 
halt mode should be exited; hence it tries to synchronize to the CAN bus (11 
consecutive recessive bits), and only then does it search for the correct conditions to 
stop.
• Trying to stop the FlexCAN immediately after reset is allowed only after basic 
initialization has been performed.
If stop with self-wake is activated, and the FlexCAN operates with single system clock per
time-quanta, then there are extreme cases in which FlexCAN's wake-up upon recessive to
dominant edge may not conform to the standard CAN protocol, in the sense that the
FlexCAN synchronization is shifted one time quanta from the required timing. This shift