Motorola MCF5281 用户手册
7-16
MCF5282 User’s Manual
MOTOROLA
Functional Description
7.3.2.25 BDM
Entering halt mode via the BDM port (by asserting the external BKPT pin) will cause the
CPU to exit any low-power mode.
CPU to exit any low-power mode.
7.3.2.26 JTAG
The JTAG (Joint Test Action Group) controller logic is clocked using the TCLK input and
is not affected by the system clock. The JTAG cannot generate an event to cause the CPU
to exit any low-power mode. Toggling TCLK during any low-power mode will increase the
system current consumption.
is not affected by the system clock. The JTAG cannot generate an event to cause the CPU
to exit any low-power mode. Toggling TCLK during any low-power mode will increase the
system current consumption.
7.3.3
Summary of Peripheral State During Low-Power Modes
The functionality of each of the peripherals and CPU during the various low-power modes
is summarized in Table 7-7. The status of each peripheral during a given mode refers to the
condition the peripheral automatically assumes when the STOP instruction is executed and
the LPCR[LPMD] field is set for the particular low-power mode. Individual peripherals
may be disabled by programming its dedicated control bits. The wakeup capability field
refers to the ability of an interrupt or reset by that peripheral to force the CPU into run
mode.
is summarized in Table 7-7. The status of each peripheral during a given mode refers to the
condition the peripheral automatically assumes when the STOP instruction is executed and
the LPCR[LPMD] field is set for the particular low-power mode. Individual peripherals
may be disabled by programming its dedicated control bits. The wakeup capability field
refers to the ability of an interrupt or reset by that peripheral to force the CPU into run
mode.
Table 7-7. CPU and Peripherals in Low-Power Modes
Module
Peripheral Status
1
/ Wakeup Capability
Wait Mode
Doze Mode
Stop Mode
CPU
Stopped
No
Stopped
No
Stopped
No
SRAM
Stopped
No
Stopped
No
Stopped
No
Flash
Stopped
No
Stopped
No
Stopped
No
System Integration Module
Enabled
Yes
3
Enabled
Yes
3
Stopped
No
SDRAM Controller
Enabled
No
Enabled
No
Stopped
No
Chip Select Module
Enabled
No
Enabled
No
Stopped
No
DMA Controller
Enabled
Yes
Enabled
Yes
Stopped
No
UART0, UART1 and UART2
Enabled
Yes
2
Enabled
Yes
2
Stopped
No
I
2
C Module
Enabled
Yes
2
Enabled
Yes
2
Stopped
No
QSPI
Enabled
Yes
2
Enabled
Yes
2
Stopped
No
DMA Timers
Enabled
Yes
2
Enabled
Yes
2
Stopped
No
Interrupt controller
Enabled
Yes
2
Enabled
Yes
2
Enabled
Yes
Fast Ethernet Controller
Enabled
Yes
2
Enabled
Yes
2
Stopped
No
I/O Ports
Enabled
No
Enabled
No
Enabled
No
Reset Controller
Enabled
Yes
3
Enabled
Yes
3
Enabled
Yes
3