Motorola MCF5281 用户手册
10-4
MCF5282 User’s Manual
MOTOROLA
68K/ColdFire Interrupt Architecture Overview
The decoded priority levels from all the interrupt controllers are logically summed together
and the highest enabled interrupt request is then encoded into a 3-bit priority level that is
sent to the processor core during this prioritization phase.
and the highest enabled interrupt request is then encoded into a 3-bit priority level that is
sent to the processor core during this prioritization phase.
10.1.1.3 Interrupt Vector Determination
Once the core has sampled for pending interrupts and begun interrupt exception processing,
it generates an interrupt acknowledge cycle (IACK). The IACK transfer is treated as a
memory-mapped byte read by the processor, and routed to the appropriate interrupt
controller. Next, the interrupt controller extracts the level being acknowledged from
address bits[4:2], and then determines the highest priority interrupt request active for that
level, and returns the 8-bit interrupt vector for that request to complete the cycle. The 8-bit
interrupt vector is formed using the following algorithm:
it generates an interrupt acknowledge cycle (IACK). The IACK transfer is treated as a
memory-mapped byte read by the processor, and routed to the appropriate interrupt
controller. Next, the interrupt controller extracts the level being acknowledged from
address bits[4:2], and then determines the highest priority interrupt request active for that
level, and returns the 8-bit interrupt vector for that request to complete the cycle. The 8-bit
interrupt vector is formed using the following algorithm:
For INTC0,
vector_number = 64 + interrupt source number
For INTC1,
vector_number = 128 + interrupt source number
Recall vector_numbers 0 - 63 are reserved for the ColdFire processor and its internal
exceptions. Thus, the following mapping of bit positions to vector numbers applies for the
INTC0:
exceptions. Thus, the following mapping of bit positions to vector numbers applies for the
INTC0:
if interrupt source 1 is active and acknowledged,
then vector_number = 65
if interrupt source 2 is active and acknowledged,
then vector_number = 66
...
if interrupt source 8 is active and acknowledged,
then vector_number = 72
if interrupt source 9 is active and acknowledged,
then vector_number = 73
...
if interrupt source 62 is active and acknowledged, then vector_number = 126
The net effect is a fixed mapping betwe
en the bit position within the source to the actual
interrupt vector number.
If there is no active interrupt source for the given level, a special “spurious interrupt” vector
(vector_number = 24) is returned and it is the responsibility of the service routine to handle
this error situation.
(vector_number = 24) is returned and it is the responsibility of the service routine to handle
this error situation.
Note this protocol implies the interrupting peripheral is not accessed during the
acknowledge cycle since the interrupt controller completely services the acknowledge.
This means the interrupt source must be explicitly disabled in the interrupt service routine.
This design provides unique vector capability for all interrupt requests, regardless of the
“complexity” of the peripheral device.
acknowledge cycle since the interrupt controller completely services the acknowledge.
This means the interrupt source must be explicitly disabled in the interrupt service routine.
This design provides unique vector capability for all interrupt requests, regardless of the
“complexity” of the peripheral device.
Vector numbers 64-71, and 91-255 are unused.