Motorola MCF5281 用户手册
MOTOROLA
Chapter 10. Interrupt Controller Modules
10-15
Register Descriptions
10.3.7 Software and Level n IACK Registers (SWIACKR,
L1IACK–L7IACK)
The eight IACK registers can be explicitly addressed via the CPU, or implicitly addressed
via a processor-generated interrupt acknowledge cycle during exception processing. In
either case, the interrupt controller’s actions are very similar.
via a processor-generated interrupt acknowledge cycle during exception processing. In
either case, the interrupt controller’s actions are very similar.
First, consider an IACK cycle to a specific level: that is, a level-n IACK. When this type of
IACK arrives in the interrupt controller, the controller examines all the currently-active
level n interrupt requests, determines the highest priority within the level, and then
responds with the unique vector number corresponding to that specific interrupt source.
The vector number is supplied as the data for the byte-sized IACK read cycle. In addition
to providing the vector number, the interrupt controller also loads the level and priority
number for the level into the IACKLPR register, where it may be retrieved later.
IACK arrives in the interrupt controller, the controller examines all the currently-active
level n interrupt requests, determines the highest priority within the level, and then
responds with the unique vector number corresponding to that specific interrupt source.
The vector number is supplied as the data for the byte-sized IACK read cycle. In addition
to providing the vector number, the interrupt controller also loads the level and priority
number for the level into the IACKLPR register, where it may be retrieved later.
Table 10-14. Interrupt Source Assignment for INTC1
Source Module
Flag
Source Description
Flag Clearing Mechanism
1-7
Not Used
8
FLEX
CAN
BUF0I
Message buffer 0 interrupt
Write BUF0I = 1 after reading BUF0I = 1
9
BUF1I
Message buffer 1 interrupt
Write BUF1I = 1 after reading BUF1I = 1
10
BUF2I
Message buffer 2 interrupt
Write BUF2I = 1 after reading BUF2I = 1
11
BUF3I
Message buffer 3 interrupt
Write BUF3I = 1 after reading BUF3I = 1
12
BUF4I
Message buffer 4 interrupt
Write BUF4I = 1 after reading BUF4I = 1
13
BUF5I
Message buffer 5 interrupt
Write BUF5I = 1 after reading BUF5I = 1
14
BUF6I
Message buffer 6 interrupt
Write BUF6I = 1 after reading BUF6I = 1
15
BUF7I
Message buffer 7 interrupt
Write BUF7I = 1 after reading BUF7I = 1
16
BUF8I
Message buffer 8 interrupt
Write BUF8I = 1 after reading BUF8I = 1
17
BUF9I
Message buffer 9 interrupt
Write BUF9I = 1 after reading BUF9I = 1
18
BUF10I
Message buffer 10 interrupt
Write BUF10I = 1 after reading BUF10I = 1
19
BUF11I
Message buffer 11 interrupt
Write BUF11I = 1 after reading BUF11I = 1
20
BUF12I
Message buffer 12 interrupt
Write BUF12I = 1 after reading BUF12I = 1
21
BUF13I
Message buffer 13 interrupt
Write BUF13I = 1 after reading BUF13I = 1
22
BUF14I
Message buffer 14 interrupt
Write BUF14I = 1 after reading BUF14I = 1
23
BUF15I
Message buffer 15 interrupt
Write BUF15I = 1 after reading BUF15I = 1
24
ERR_INT Error interrupt
Read error bits in ESR or write ERR_INT = 0
25
BOFF_INT Bus-off interrupt
Write BOFF_INT = 0
26
WAKE_INT Wake-up interrupt
Write WAKE_INT = 0
27-63
Not used