Motorola MCF5281 用户手册
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Chapter 10. Interrupt Controller Modules
10-17
Low-Power Wakeup Operation
10.5 Low-Power Wakeup Operation
The System Control Module (SCM) contains an 8-bit low-power interrupt control register
(LPICR) used explicitly for controlling the low-power stop mode. This register must
explicitly be programmed by software to enter low-power mode.
(LPICR) used explicitly for controlling the low-power stop mode. This register must
explicitly be programmed by software to enter low-power mode.
Each interrupt controller provides a special combinatorial logic path to provide a special
wake-up signal to exit from the low-power stop mode. This special mode of operation
works as follows:
wake-up signal to exit from the low-power stop mode. This special mode of operation
works as follows:
• First, LPICR[6:4] is loaded with the mask level that will be specified while the core
is in stop mode. LPICR[7] must be set to enable this mode of operation.
NOTE
The wakeup mask level taken from LPICR[6:4] is adjusted by
hardware to allow a level 7 IRQ to generate a wakeup. That is,
the wakeup mask value used by the interrupt controller must be
in the range of 0–6.
hardware to allow a level 7 IRQ to generate a wakeup. That is,
the wakeup mask value used by the interrupt controller must be
in the range of 0–6.
• Second, the processor executes a STOP instruction which places it in stop mode.
Once the processor is stopped, each interrupt controller enables a special logic path
which evaluates the incoming interrupt sources in a purely combinatorial path; that
is, there are no clocked storage elements. If an active interrupt request is asserted and
the resulting interrupt level is greater than the mask value contained in LPICR[6:4],
then each interrupt controller asserts the wake-up output signal, which is routed to
the SCM where it is combined with the wakeup signals from the other interrupt
controller and then to the PLL module to re-enable the device’s clock trees and
resume processing.
which evaluates the incoming interrupt sources in a purely combinatorial path; that
is, there are no clocked storage elements. If an active interrupt request is asserted and
the resulting interrupt level is greater than the mask value contained in LPICR[6:4],
then each interrupt controller asserts the wake-up output signal, which is routed to
the SCM where it is combined with the wakeup signals from the other interrupt
controller and then to the PLL module to re-enable the device’s clock trees and
resume processing.