Motorola MCF5281 用户手册

MOTOROLA

Chapter 14.  Signal Descriptions  

14-7

Table 14-2 lists signals in alphabetical order by abbreviated name.

Development serial 
output/Test data

DSO/TDO

Provides single-bit communication for 
debug module responses (DSO). 
Provides serial data port for outputting 
JTAG logic data (TDO).

O

Test clock

TCLK

JTAG test logic clock.

I

Debug data

DDATA[3:0]

Display captured processor 
addresses, data, and breakpoint 
status.

O

Processor status 
outputs

PST[3:0]

Indicate core status.

O

Test

TEST

Reserved, should be connected to 
VSS.

I

QADC analog reference VRH, VRL

High (VRH) and low (VRL) reference 
potentials for the analog converter.

Ground

QADC analog supply

VDDA, VSSA

Isolate the QADC analog circuitry 
from digital power supply noise.

I

PLL analog supply

VDDPLL, VSSPLL Isolate the PLL analog circuitry from 

digital power supply noise.

I

QADC positive supply

VDDH

Supplies positive power to the ESD 
structures in the QADC pads.

I

Flash erase/program
power

VPP

Used for Flash stress testing.

I

Flash array power
and ground

VDDF, VSSF

Supply power and ground to Flash 
array.

I

Standby power

VSTBY

Provides standby voltage to RAM 
array if VDD is lost.

I

Positive supply

VDD

Supplies positive power to the core 
logic and I/O pads.

I

Ground

VSS

Negative supply.