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Chapter 14.  Signal Descriptions  

14-9

EMDIO

Transfers control information between the external PHY and 
the media access controller.

I/O

ERXCLK

Provides a timing reference for ERXDV, ERXD[3:0], and 
ERXER.

I

ERXD[3:1]

Contain the Ethernet input data transferred from the PHY to the 
media access controller (when ERXDV is asserted in MII 
mode).

I

ERXD0

Ethernet input data transferred from the PHY to the media 
access controller (when ERXDV is asserted).

I

ERXDV

Asserted to indicate that the PHY has valid nibbles present on 
the MII.

I

ERXER

Indicates (when asserted with ERXDV) that the PHY has 
detected an error in the current frame.

I

ETXCLK

Provides a timing reference for ETXEN, ETXD[3:0], and 
ETXER.

I

ETXD[3:1]

Contain the serial output Ethernet data.

O

ETXD0

Serial output Ethernet data.

O

ETXEN

Indicates when valid nibbles are present on the MII.

O

ETXER

Asserted (for one or more E_TXCLKs while ETXEN is also 
asserted) to cause the PHY to send one or more illegal 
symbols.

O

EXTAL

Driven by an external clock except when used as a connection 
to the external crystal.

I

VDDF, VSSF

Supply power and ground to Flash array.

I

VPP

Used for Flash stress testing.

I

GPTA[3:0]

Provide the external interface to the timer A functions.

I/O

GPTB[3:0]

Provide the external interface to the timer B functions.

I/O

Ground

Negative supply.

IRQ[7:1]

External interrupt sources.

I

JTAG_EN

Selects between multiplexed debug module and JTAG signals 
at reset.

I

OE

Indicates when an external device can drive data on the bus.

O

VDDPLL

Isolate the PLL analog circuitry from digital power supply noise.

I

VDD

Supplies positive power to the core logic and I/O pads.

I

PST[3:0]

Indicate core status.

O

VRH, VRL

High (VRH) and low (VRL) reference potentials for the analog 
converter.

I

VDDA, VSSA

Isolate the QADC analog circuitry from digital power supply 
noise.

I