Motorola MCF5281 用户手册

15-14

MOTOROLA

 

the port size of the associated SDRAM. The primary cycle of the transfer generates the

ACTV

 and 

READ

 or 

WRITE

 commands; secondary cycles generate only 

READ

 or 

WRITE

commands. As soon as the transfer completes, the 

PALL

 command is generated to prepare

for the next access.

Note that in synchronous operation, burst mode and address incrementing during burst
cycles are controlled by the MCF5282 DRAM controller. Thus, instead of the SDRAM
enabling its internal burst incrementing capability, the MCF5282 controls this function.
This means that the burst function that is enabled in the mode register of SDRAMs must be
disabled when interfacing to the MCF5282.

Figure 15-6 shows a burst read operation. In this example, DACR[CASL] = 01 for an
SRAS-to-SCAS delay (t

RCD

) of 2 system clock cycles. Because t

RCD 

is equal to the read

CAS latency (SCAS assertion to data out), this value is also 2 system clock cycles. Notice
that 

NOP

s are executed until the last data is read. A 

PALL

 command is executed one cycle

after the last data transfer.

Figure 15-7 shows the burst write operation. In this example, DACR[CASL] = 01, which
creates an SRAS-to-SCAS delay (t

RCD

) of 2 system clock cycles. Note that data is available

upon SCAS assertion and a burst write cycle completes two cycles sooner than a burst read
cycle with the same t

RCD. 

The next bus cycle is initiated sooner, but cannot begin an

SDRAM cycle until the precharge-to-

ACTV

 delay completes.

A[31:0]

SRAS

SCAS

DRAMW

D[31:0]

t

CASL

 = 2

ACTV

READ

NOP

NOP

SDRAM_CS[0] or [1]

BS[3:0]

NOP

PALL

Row

Column

Column

Column

Column

t

RCD

 = 2

t

EP

CLKOUT

READ

READ

READ