Motorola MCF5281 用户手册

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Chapter 16.  DMA Controller Module  

16-7

The DMA does not maintain coherency with the MCF5282
cache. Therefore, DMAs should not transfer data to cacheable
memory unless software is used to maintain the cache
coherency.

The DMA should not be used to write data to the UART
transmit FIFO in cycle steal mode. When the UART interrupt
is used as a DMA request it does not negate fast enough to get
a single transfer. The UART transmit FIFO only has one entry
so the data from the second byte would be lost. 

BCRn, shown in Figure 16-6 and Figure 16-7, hold the number of bytes yet to be
transferred for a given block. The offset within the memory map is based on the value of
MPARK[BCR24BIT]. BCRn decrements on the successful completion of the address
transfer of a write transfer. BCRn decrements by 1, 2, 4, or 16 for byte, word, longword, or
line accesses, respectively.

Figure 16-6 shows BCRn for BCR24BIT = 1.

Figure 16-6. Byte Count Registers (BCRn)—BCR24BIT = 1

Figure 16-7 shows BCRn for BCR24BIT = 0. 

Figure 16-7. Byte Count Registers (BCRn)—BCR24BIT = 0

DSRn[DONE], shown in Figure 16-9, is set when the block transfer is complete.

31

24 23

0

Field

—

BCR

Reset

—

0000_0000_0000_0000_0000_0000

R/W

R/W

Address

IPSBAR + 0x10C, 0x14C, 0x18C, 0x1CC

15

0

Field

BCR

Reset

0000_0000_0000_0000

R/W

R/W

Address

IPSBAR + 0x10C, 0x14C, 0x18C, 0x1CC