Motorola MCF5281 用户手册
16-8
MCF5282 User’s Manual
MOTOROLA
DMA Controller Module Programming Model
When a transfer sequence is initiated and BCRn[BCR] is not a multiple of 16, 4, or 2 when
the DMA is configured for line, longword, or word transfers, respectively, DSRn[CE] is set
and no transfer occurs. See Section 16.4.5, “DMA Status Registers (DSR0–DSR3).”
the DMA is configured for line, longword, or word transfers, respectively, DSRn[CE] is set
and no transfer occurs. See Section 16.4.5, “DMA Status Registers (DSR0–DSR3).”
16.4.4 DMA Control Registers (DCR0–DCR3)
DCRn, shown in Figure 16-8, is used for configuring the DMA controller module. Note
that DCRn[AT] is available only if MPARK[BCR24BIT] is set. See Section 8.5.3, “Bus
Master Park Register (MPARK)” for more information.
that DCRn[AT] is available only if MPARK[BCR24BIT] is set. See Section 8.5.3, “Bus
Master Park Register (MPARK)” for more information.
Table 16-3 describes DCRn fields.
31
30
29
28
27
25
24
23
22
21
20
19
18
17
16
Field INT EEXT
CS
AA
BWC
—
—
SINC
SSIZE
DINC
DSIZE
START
Reset
0000_0000_0000_0000
R/W
R/W
15
14
0
Field AT
1
1
Available only if BCR24BIT = 1, otherwise reserved.
—
Reset
0
N/A
R/W
R/W
Address
IPSBAR + 0x108, 0x148, 0x188, 0x1C8
Figure 16-8. DMA Control Registers (DCRn)
Table 16-3. DCRn Field Descriptions
Bits
Name
Description
31
INT
Interrupt on completion of transfer. Determines whether an interrupt is generated by completing a transfer or by
the occurrence of an error condition.
0 No interrupt is generated.
1 Internal interrupt signal is enabled.
the occurrence of an error condition.
0 No interrupt is generated.
1 Internal interrupt signal is enabled.
30
EEXT Enable external request. Care should be taken because a collision can occur between the START bit and DREQ
when EEXT = 1.
0 External request is ignored.
1 Enables external request to initiate transfer. The internal request (initiated by setting the START bit) is
0 External request is ignored.
1 Enables external request to initiate transfer. The internal request (initiated by setting the START bit) is
always enabled.
29
CS
Cycle steal.
0 DMA continuously makes read/write transfers until the BCR decrements to 0.
1 Forces a single read/write transfer per request. The request may be internal by setting the START bit, or
0 DMA continuously makes read/write transfers until the BCR decrements to 0.
1 Forces a single read/write transfer per request. The request may be internal by setting the START bit, or
external by asserting DREQ.
28
AA
Auto-align. AA and SIZE determine whether the source or destination is auto-aligned, that is, transfers are
optimized based on the address and size. See Section 16.5.4.1, “Auto-Alignment.”
0 Auto-align disabled
1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination
optimized based on the address and size. See Section 16.5.4.1, “Auto-Alignment.”
0 Auto-align disabled
1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination
accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment
is enabled, the appropriate address register increments, regardless of DINC or SINC.
is enabled, the appropriate address register increments, regardless of DINC or SINC.