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Chapter 20.  General Purpose Timer Modules (GPTA and GPTB)  

20-21

Reset initializes the GPT registers to a known startup state as described in Section 20.5,
“Memory Map and Registers.”

Table 20-24 lists the interrupt requests generated by the timer.

1

1

1

X

<> 0

0

Out

OC action Output compare Pin driven by OC action

(5)

1

0

1

X

X

1

Out

OC action/

OC3Dn

Output compare

(ch 3)

Pin readable only if DDR = 0

 6

1

1

1

X

X

1

Out

OC action/

OC3Dn

Output compare/

OC3Dn

(ch 3)

Pin driven by channel OC action and 
OC3Dn via channel 3 OC

(6)

1

When DDR set the pin as input (0), reading the data register will return the state of the pin. When DDR set the pin as output (1), 
reading the data register will return the content of the data latch. Pin conditions such as rising or falling edges can trigger an input 
capture on a pin configured as an input.

2

OMn/OLn bit pairs select the output action to be taken as a result of a successful output compare. When either OMn or OLn is 
set and the IOSn bit is set, the pin is an output regardless of the state of the corresponding DDR bit.

3

Setting an OC3M bit configures the corresponding PORTTn pin to be output. OC3Mn makes the PORTTn pin an output regardless 
of the data direction bit when the pin is configured for output compare (IOSn = 1). The OC3Mn bits do not change the state of the 
PORTTnDDR bits.

4

X = Don’t care

5

An output compare overrides the data direction bit of the output compare pin but does not change the state of the data direction 
bit. Enabling output compare disables data register drive of the pin.

6

A successful output compare on channel 3 causes an output value determined by OC3Dn value to temporarily override the output 
compare pin state of any other output compare channel.The next OC action for the specific channel will still be output to the pin. 
A channel 3 output compare can cause bits in the output compare 3 data register to transfer to the GPT port data register, 
depending on the output compare 3 mask register.

Channel 3 IC/OC

C3F

C3I

Channel 2 IC/OC

C2F

C2I

Channel 1 IC/OC

C1F

C1I

Channel 0 IC/OC

C0F

C0I

PA overflow

PAOVF

PAOVI

PA input

PAIF

PAI

Timer overflow

TOF

TOI