Motorola MCF5281 用户手册
MOTOROLA
Chapter 23. UART Modules
23-15
Register Descriptions
NOTE
The minimum value that can be loaded on the concatenation of
UBG1n with UBG2n is 0x0002. Both UBG1n and UBG2n are
write-only and cannot be read by the CPU.
UBG1n with UBG2n is 0x0002. Both UBG1n and UBG2n are
write-only and cannot be read by the CPU.
23.3.12 UART Input Port Register (UIPn)
The UIPn registers, shown in Figure 23-14, show the current state of the CTS input.
Table 23-10 describes UIPn fields.
23.3.13 UART Output Port Command Registers (UOP1n/UOP0n)
The RTS output can be asserted by writing a 1 to UOP1n[RTS] and negated by writing a 1
to UOP0n[RTS]. See Figure 23-15.
to UOP0n[RTS]. See Figure 23-15.
Table 23-11 describes UOP1 and UOP0 fields.
7
1
0
Field
—
CTS
Reset
1111_1111
R/W
R
Address
IPSBAR + 0x234 (UIP0), 0x274 (UIP1), 0x2B4 (UIP2)
Figure 23-14. UART Input Port Register (UIPn)
Table 23-10. UIPn Field Descriptions
Bits
Name
Description
7–1
—
Reserved, should be cleared.
0
CTS
Current state of clear-to-send. The CTS value is latched and reflects the state of the input pin when UIPn
is read. Note: This bit has the same function and value as UIPCRn[RTS].
0 The current state of the CTS input is logic 0.
1 The current state of the CTS input is logic 1.
is read. Note: This bit has the same function and value as UIPCRn[RTS].
0 The current state of the CTS input is logic 0.
1 The current state of the CTS input is logic 1.
7
1
0
Field
—
RTS
Reset
0000_0000
R/W
W
Addr UART0: IPSBAR + 0x238 (UOP1), 0x23C (UOP0); UART1 0x278 (UOP1), 0x27C (UOP0); UART2 0x2B8 (UOP1) 0x2BC
(UOP0)
Figure 23-15. UART Output Port Command Registers (UOP1n/UOP0n)