Motorola MCF5281 用户手册
MOTOROLA
Chapter 23. UART Modules
23-13
Register Descriptions
23.3.9 UART Auxiliary Control Register (UACRn)
Table 23-8 describes UACRn fields.
23.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)
The UISRs, shown in Figure 23-11, provide status for all potential interrupt sources. UISRn
contents are masked by UIMRn. If corresponding UISRn and UIMRn bits are set, the
internal interrupt output is asserted. If a UIMRn bit is cleared, the state of the corresponding
UISRn bit has no effect on the output.
contents are masked by UIMRn. If corresponding UISRn and UIMRn bits are set, the
internal interrupt output is asserted. If a UIMRn bit is cleared, the state of the corresponding
UISRn bit has no effect on the output.
NOTE
True status is provided in the UISRn regardless of UIMRn
settings. UISRn is cleared when the UART module is reset.
settings. UISRn is cleared when the UART module is reset.
7
1
0
Field
—
IEC
Reset
0000_0000
R/W
W
Address
IPSBAR + 0x210 (UACR0), 0x250 (UACR1), 0x290 (UACR2)
Figure 23-10. UART Auxiliary Control Register (UACRn)
Table 23-8. UACRn Field Descriptions
Bits
Name
Description
7–1
—
Reserved, should be cleared.
0
IEC
Input enable control.
0 Setting the corresponding UIPCRn bit has no effect on UISRn[COS].
1 UISRn[COS] is set and an interrupt is generated when the UIPCRn[COS] is set by an external transition
0 Setting the corresponding UIPCRn bit has no effect on UISRn[COS].
1 UISRn[COS] is set and an interrupt is generated when the UIPCRn[COS] is set by an external transition
on the CTS input (if UIMRn[COS] = 1).
7
6
3
2
1
0
UIMR
Field
COS
—
DB
FFULL/RxRDY
TxRDY
UISR
Field
COS
—
DB
FFULL/RxRDY
TxRDY
Reset
0000_0000
R/W
Read only for status, write only for mask
Address
IPSBAR + 0x214 (UISR0), 0x254 (UISR1), 0x294 (UISR2)
Figure 23-11. UART Interrupt Status/Mask Registers (UISRn/UIMRn)