Motorola MCF5281 用户手册

27-4

MOTOROLA

 

• Aborts the conversion sequence in progress
• Makes the data direction register (DDRQA), port data registers (PORTQA and 

PORTQB), control registers (QACR2, QACR1, and QACR0) and the status 
registers (QASR1 and QASR0) read-only. Only the module configuration register 
(QADCMCR) remains writable.

• Makes the RAM inaccessible, so that valid data cannot be read from RAM (result 

word table and CCW) or written to RAM (result word table and CCW)

• Resets QACR1, QACR2, QASR0, and QASR1
• Holds the QADC periodic/interval timer in reset

Because the bias currents to the analog circuit are turned off in stop mode, the QADC
requires some recovery time (t

SR

) to stabilize the analog circuits.

The QADC uses the external signals shown in Figure 27-2. There are eight channel/port
signals that can support up to 18 channels when external multiplexing is used (including
internal channels). All of the channel signals also have some general-purpose input or
input/output (GPIO) functionality. In addition, there are also two analog reference signals
and two analog submodule power signals.

The QADC has external trigger inputs and multiplexer outputs that are shared with some
of the analog input signals.

The four port QA signals can be used as analog inputs or as a bidirectional 4-bit digital
input/output port.

When used as analog inputs, the four port QA signals are referred to as AN[56:55, 53:52].