Motorola MCF5281 用户手册
27-6
MCF5282 User’s Manual
MOTOROLA
Signals
27.4.2.2 Port QB Digital I/O Signals
Port QB signals are referred to as PQB[3:0] when used as a 4-bit digital input/output port.
In addition to functioning as analog input signals, the port QB signals are also connected to
the input of a synchronizer during reads and may be used as general-purpose digital inputs
when the applied voltages meet V
In addition to functioning as analog input signals, the port QB signals are also connected to
the input of a synchronizer during reads and may be used as general-purpose digital inputs
when the applied voltages meet V
IH
and V
IL
requirements.
Each port QB signal is configured as an input or output by programming the port data
direction register (DDRQB). The digital input signal states are read from the port QB data
register (PORTQB) when DDRQB specifies that the signals are inputs. The digital data in
PORTQB is driven onto the port QB signals when the corresponding bits in DDRQB
specify output. See Section 27.6.4.
direction register (DDRQB). The digital input signal states are read from the port QB data
register (PORTQB) when DDRQB specifies that the signals are inputs. The digital data in
PORTQB is driven onto the port QB signals when the corresponding bits in DDRQB
specify output. See Section 27.6.4.
27.4.3 External Trigger Input Signals
The QADC has two external trigger signals, ETRIG2 and ETRIG1. Each external trigger
input is associated with one of the scan queues, queue 1 or queue 2. The assignment of
ETRIG[2:1] to a queue is made by the TRG bit in QADC control register 0 (QACR0).
When TRG = 0, ETRIG1 triggers queue 1 and ETRIG2 triggers queue 2. When TRG = 1,
ETRIG1 triggers queue 2 and ETRIG2 triggers queue 1. See Section 27.6.5 “Control
Registers.”
input is associated with one of the scan queues, queue 1 or queue 2. The assignment of
ETRIG[2:1] to a queue is made by the TRG bit in QADC control register 0 (QACR0).
When TRG = 0, ETRIG1 triggers queue 1 and ETRIG2 triggers queue 2. When TRG = 1,
ETRIG1 triggers queue 2 and ETRIG2 triggers queue 1. See Section 27.6.5 “Control
Registers.”
27.4.4 Multiplexed Address Output Signals
In non-multiplexed mode, the QADC analog input signals are connected to an internal
multiplexer which routes the analog signals into the internal A/D converter.
multiplexer which routes the analog signals into the internal A/D converter.
In externally multiplexed mode, the QADC allows automatic channel selection through up
to four external 4-to-1 multiplexer chips. The QADC provides a 2-bit multiplexed address
output to the external multiplexer chips to allow selection of one of four inputs. The
multiplexed address output signals, MA1 and MA0, can be used as multiplexed address
output bits or as general-purpose I/O when external multiplexed mode is not being used.
to four external 4-to-1 multiplexer chips. The QADC provides a 2-bit multiplexed address
output to the external multiplexer chips to allow selection of one of four inputs. The
multiplexed address output signals, MA1 and MA0, can be used as multiplexed address
output bits or as general-purpose I/O when external multiplexed mode is not being used.
MA[1:0] are used as the address inputs for up to four 4-channel multiplexer chips. Because
the MA[1:0] signals are digital outputs in multiplexed mode, the state of their
corresponding data direction bits in DDRQA is ignored.
the MA[1:0] signals are digital outputs in multiplexed mode, the state of their
corresponding data direction bits in DDRQA is ignored.
27.4.5 Multiplexed Analog Input Signals
In external multiplexed mode, four of the port QB signals are redefined so that each
represent four analog input channels. See Table 27-1.
represent four analog input channels. See Table 27-1.