Motorola MCF5281 用户手册
27-12
MCF5282 User’s Manual
MOTOROLA
Register Descriptions
15
14
13
12
11
8
Field
MUX
—
TRG
—
Reset
0000_0000
R/W:
R/W
R
R/W
R
7
6
5
4
3
2
1
0
Field
—
QPR6
QPR5
QPR4
QPR3
QPR2
QPR1
QPR0
Reset
0001_0011
R/W:
R
R/W
Address
IPSBAR + 0x19_000a, 0x19_000b
Figure 27-8. QADC Control Register 0 (QACR0)
Table 27-4. QACR0 Field Descriptions
Bit(s)
Name
Description
15
MUX
Externally multiplexed mode. Configures the QADC for operation in externally multiplexed
mode, which affects the interpretation of the channel numbers and forces the MA[1:0] signals
to be outputs.
1 Externally multiplexed, up to 18 possible channels
0 Internally multiplexed, up to 8 possible channels
mode, which affects the interpretation of the channel numbers and forces the MA[1:0] signals
to be outputs.
1 Externally multiplexed, up to 18 possible channels
0 Internally multiplexed, up to 8 possible channels
14–13
—
Reserved, should be cleared.
12
TRG
Trigger assignment. Determines the queue assignment of the ETRIG[2:1] signals.
1 ETRIG1 triggers queue 2; ETRIG2 triggers queue 1.
0 ETRIG1 triggers queue 1; ETRIG2 triggers queue 2.
1 ETRIG1 triggers queue 2; ETRIG2 triggers queue 1.
0 ETRIG1 triggers queue 1; ETRIG2 triggers queue 2.
11–7
—
Reserved, should be cleared.
6–0
QPR
Prescaler clock divider. Selects the system clock divisor to generate the QADC clock as
Table 27-5 shows. The resulting QADC clock rate can be given as:
Table 27-5 shows. The resulting QADC clock rate can be given as:
where:
1
≤ QPR[6:0] ≤ 127.
If QPR[6:0] = 0, then the QPR register field value is read as a 1 and the prescaler divisor is 2.
The prescaler should be selected so that the QADC clock rate is within the required f
The prescaler should be selected so that the QADC clock rate is within the required f
QCLK
range. See MCF5282 Electrical Characteristics.
f
QCLK
=
f
SYS
2(QPR[6:0] + 1)