Motorola MCF5281 用户手册
27-10
MCF5282 User’s Manual
MOTOROLA
Register Descriptions
Note: The reset value for these fields is the current signal state if DDR is an input; otherwise, they are undefined.
27.6.4 Port QA and QB Data Direction Register
(DDRQA and DDRQB)
DDRQA and DDRQB are associated with port QA and QB digital I/O signals. Setting a bit
in these registers configures the corresponding signal as an output. Clearing a bit in these
registers configures the corresponding signal as an input. During QADC initialization, port
QA and QB signals that will be used as direct or multiplexed analog inputs must have their
corresponding data direction register bits cleared. When a port QA or QB signal that is
programmed as an output is selected for analog conversion, the voltage sampled is that of
the output digital driver as influenced by the load.
in these registers configures the corresponding signal as an output. Clearing a bit in these
registers configures the corresponding signal as an input. During QADC initialization, port
QA and QB signals that will be used as direct or multiplexed analog inputs must have their
corresponding data direction register bits cleared. When a port QA or QB signal that is
programmed as an output is selected for analog conversion, the voltage sampled is that of
the output digital driver as influenced by the load.
When the MUX (externally multiplexed) bit is set in QACR0, the data direction register
settings are ignored for the bits corresponding to PQA[1:0], and the two multiplexed
address (MA[1:0]) output signals. The MA[1:0] signals are forced to be digital outputs,
regardless of their data direction setting, and the multiplexed address outputs are driven.
The data returned during a port data register read is the value of the MA[1:0] signals,
regardless of their data direction setting.
settings are ignored for the bits corresponding to PQA[1:0], and the two multiplexed
address (MA[1:0]) output signals. The MA[1:0] signals are forced to be digital outputs,
regardless of their data direction setting, and the multiplexed address outputs are driven.
The data returned during a port data register read is the value of the MA[1:0] signals,
regardless of their data direction setting.
Similarly, when the external trigger signals are assigned to port signals and external trigger
queue operating mode is selected, the data direction setting for the corresponding signals,
PQA3 and/or PQA4, is ignored. The port signals are forced to be digital inputs for ETRIG1
and/or ETRIG2. The data returned during a port data register read is the value of the
ETRIG[2:1] signals, regardless of their data direction setting.
queue operating mode is selected, the data direction setting for the corresponding signals,
PQA3 and/or PQA4, is ignored. The port signals are forced to be digital inputs for ETRIG1
and/or ETRIG2. The data returned during a port data register read is the value of the
ETRIG[2:1] signals, regardless of their data direction setting.
7
6
5
4
3
2
1
0
Field
—
PQA4
(AN56)
(ETRIG2)
PQA3
(AN55)
(ETRIG1)
—
PQA1
(AN53)
(MA1)
PQA0
(AN52)
(MA0)
Reset
000
See Note
0
See Note
R/W:
R
R/W
R
R/W
Address
IPSBAR + 0x19_0006
Figure 27-4. QADC Port QA Data Register (PORTQA)
7
6
5
4
3
2
1
0
Field
—
PQB3
(AN3)
(ANZ)
PQB2
(AN2)
(ANY)
PQA1
(AN1)
(ANX)
PQA0
(AN0)
(ANW)
Reset
0000
See Note
R/W:
R
R/W
Address
IPSBAR + 0x19_0007
Figure 27-5. QADC Port QB Data Register (PORTQB)