Motorola MCF5281 用户手册
MOTOROLA
Chapter 29. Debug Support
29-3
Real-Time Trace Support
29.3 Real-Time Trace Support
Real-time trace, which defines the dynamic execution path, is a fundamental debug
function. The ColdFire solution is to include a parallel output port providing encoded
processor status and data to an external development system. This port is partitioned into
two 4-bit nibbles: one nibble allows the processor to transmit processor status, (PST), and
the other allows operand data to be displayed (debug data, DDATA). The processor status
may not be related to the current bus transfer.
function. The ColdFire solution is to include a parallel output port providing encoded
processor status and data to an external development system. This port is partitioned into
two 4-bit nibbles: one nibble allows the processor to transmit processor status, (PST), and
the other allows operand data to be displayed (debug data, DDATA). The processor status
may not be related to the current bus transfer.
External development systems can use PST outputs with an external image of the program
to completely track the dynamic execution path. This tracking is complicated by any
change in flow, especially when branch target address calculation is based on the contents
of a program-visible register (variant addressing). DDATA outputs can be configured to
display the target address of such instructions in sequential nibble increments across
multiple processor clock cycles, as described in Section 29.3.1, “Begin Execution of Taken
Branch (PST = 0x5).” Two 32-bit storage elements form a FIFO buffer connecting the
processor’s high-speed local bus to the external development system through PST[3:0] and
DDATA[3:0]. The buffer captures branch target addresses and certain data values for
eventual display on the DDATA port, one nibble at a time starting with the least significant
bit (lsb).
to completely track the dynamic execution path. This tracking is complicated by any
change in flow, especially when branch target address calculation is based on the contents
of a program-visible register (variant addressing). DDATA outputs can be configured to
display the target address of such instructions in sequential nibble increments across
multiple processor clock cycles, as described in Section 29.3.1, “Begin Execution of Taken
Branch (PST = 0x5).” Two 32-bit storage elements form a FIFO buffer connecting the
processor’s high-speed local bus to the external development system through PST[3:0] and
DDATA[3:0]. The buffer captures branch target addresses and certain data values for
eventual display on the DDATA port, one nibble at a time starting with the least significant
bit (lsb).
Execution speed is affected only when both storage elements contain valid data to be
dumped to the DDATA port. The core stalls until one FIFO entry is available.
dumped to the DDATA port. The core stalls until one FIFO entry is available.
Table 29-2 shows the encoding of these signals.
Table 29-2. Processor Status Encoding
PST[3:0]
Definition
Hex
Binary
0x0
0000
Continue execution. Many instructions execute in one processor cycle. If an instruction requires more processor
clock cycles, subsequent clock cycles are indicated by driving PST outputs with this encoding.
clock cycles, subsequent clock cycles are indicated by driving PST outputs with this encoding.
0x1
0001
Begin execution of one instruction. For most instructions, this encoding signals the first processor clock cycle of
an instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA instructions,
generate different encodings.
an instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA instructions,
generate different encodings.
0x2
0010
Reserved
0x3
0011
Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor to enter user
mode.
mode.
0x4
0100
Begin execution of PULSE and WDDATA instructions. PULSE defines logic analyzer triggers for debug and/or
performance analysis. WDDATA lets the core write any operand (byte, word, or longword) directly to the
DDATA port, independent of debug module configuration. When WDDATA is executed, a value of 0x4 is
signaled on the PST port, followed by the appropriate marker, and then the data transfer on the DDATA port.
Transfer length depends on the WDDATA operand size.
performance analysis. WDDATA lets the core write any operand (byte, word, or longword) directly to the
DDATA port, independent of debug module configuration. When WDDATA is executed, a value of 0x4 is
signaled on the PST port, followed by the appropriate marker, and then the data transfer on the DDATA port.
Transfer length depends on the WDDATA operand size.
0x5
0101
Begin execution of taken branch. For some opcodes, a branch target address may be displayed on DDATA
depending on the CSR settings. CSR also controls the number of address bytes displayed, indicated by the PST
marker value preceding the DDATA nibble that begins the data output. See Section 29.3.1, “Begin Execution of
Taken Branch (PST = 0x5).”
depending on the CSR settings. CSR also controls the number of address bytes displayed, indicated by the PST
marker value preceding the DDATA nibble that begins the data output. See Section 29.3.1, “Begin Execution of
Taken Branch (PST = 0x5).”
0x6
0110
Reserved