Motorola MCF5281 用户手册
29-22
MCF5282 User’s Manual
MOTOROLA
Background Debug Mode (BDM)
29.5.3.2 Command Sequence Diagrams
The command sequence diagram in Figure 29-16 shows serial bus traffic for commands.
Each bubble represents a 17-bit bus transfer. The top half of each bubble indicates the data
the development system sends to the debug module; the bottom half indicates the debug
module’s response to the previous development system commands. Command and result
transactions overlap to minimize latency.
Each bubble represents a 17-bit bus transfer. The top half of each bubble indicates the data
the development system sends to the debug module; the bottom half indicates the debug
module’s response to the previous development system commands. Command and result
transactions overlap to minimize latency.
Figure 29-16. Command Sequence Diagram
The sequence is as follows:
• In cycle 1, the development system command is issued (
READ
in this example). The
debug module responds with either the low-order results of the previous command
or a command complete status of the previous command, if no results are required.
or a command complete status of the previous command, if no results are required.
• In cycle 2, the development system supplies the high-order 16 address bits. The
debug module returns a not-ready response unless the received command is decoded
as unimplemented, which is indicated by the illegal command encoding. If this
occurs, the development system should retransmit the command.
as unimplemented, which is indicated by the illegal command encoding. If this
occurs, the development system should retransmit the command.
NOTE:
A not-ready response can be ignored except during a
memory-referencing cycle. Otherwise, the debug module can
accept a new serial transfer after 32 processor clock periods.
memory-referencing cycle. Otherwise, the debug module can
accept a new serial transfer after 32 processor clock periods.
• In cycle 3, the development system supplies the low-order 16 address bits. The
debug module always returns a not-ready response.
XXX
’NOT READY’
READ (LONG)
???
MS ADDR
’NOT READY’
LS ADDR
’NOT READY’
NEXT CMD
’NOT READY’
NEXT CMD
’NOT READY’
NEXT CMD
LS RESULT
Commands transmitted to the debug module
Command code transmitted during this cycle
High-order 16 bits of memory address
Low-order 16 bits of memory address
Non-serial-related
Next
Command
Code
Sequence taken if operation
has not completed
has not completed
activity
READ
MEMORY
LOCATION
XXX
BERR
XXX
MS RESULT
XXX
’ILLEGAL’
Responses from the debug module
Results from previous command
Sequence taken if illegal command
is received by debug module
is received by debug module
Data used from this transfer
Sequence taken if bus error
occurs on memory access
occurs on memory access
High- and low-order 16 bits of result