Motorola MCF5281 用户手册

MOTOROLA

Chapter 29.  Debug Support  

29-23

• At the completion of cycle 3, the debug module initiates a memory read operation. 

Any serial transfers that begin during a memory access return a not-ready response.

• Results are returned in the two serial transfer cycles after the memory access 

completes. For any command performing a byte-sized memory read operation, the 
upper 8 bits of the response data are undefined and the referenced data is returned in 
the lower 8 bits. The next command’s opcode is sent to the debug module during the 
final transfer. If a memory or register access is terminated with a bus error, the error 
status (S = 1, DATA = 0x0001) is returned instead of result data.

The following sections describe the commands summarized in Table 29-17. 

The BDM status bit (S) is 0 for normally completed
commands; S = 1 for illegal commands, not-ready responses,
and transfers with bus-errors. Section 29.5.2, “BDM Serial
Interface,” describes the receive packet format.

Motorola reserves unassigned command opcodes for future expansion. Unused command
formats in any revision level perform a 

NOP

 and return an illegal command response.

Read the selected address or data register and return the 32-bit result. A bus error response
is returned if the CPU core is not halted.

Command/Result Formats:

Command Sequence:

Operand Data:

None

Result Data:

The contents of the selected register are returned as a longword 
value, most-significant word first.

15

12

11

8

7

4

3

2

0

Command

0x2

0x1

0x8

A/D

Register

Result

D[31:16]

D[15:0]

RAREG/RDREG

???

NEXT CMD

LS RESULT

NEXT CMD

’NOT READY’

XXX

BERR

XXX

MS RESULT