Motorola MCF5281 用户手册

30-6

MOTOROLA

 

At reset, RCON determines the default operation of certain chip functions. All default
functions defined by the RCON values can only be overridden during reset configuration
(see Section 30.6.1, “Reset Configuration”) if the external RCON pin is asserted. RCON is
a read-only register.

3

BME

Bus monitor enable. This read/write bit enables the bus monitor to operate during external bus cycles.
0 Bus monitor disabled for external bus cycles.
1 Bus monitor enabled for external bus cycles.
Table 30-2 shows the read/write accessibility of this write-once bit.

2–0

BMT

Bus monitor timing. This field selects the timeout period (in system clocks) for the bus monitor.
000  65536
001  32768
010  16384
011  8192
100  4096
101  2048
110  1024
111  512
Table 30-2 shows the read/write accessibility of this write-once bit.

15

10

9

8

7

6

5

4

3

2

1

0

Field

—

RCSC

RPLLSEL RPLLREF RLOAD

BOOTPS

BOOTSEL

—

MODE

Reset

0000_0000_1110_0000

R/W

R

Address

IPSBAR + 0x11_0008

15–10

—

Reserved, should be cleared.

9–8

RCSC

Chip select configuration. Reflects the default chip select configuration. The default function of the 
chip select configuration can be overridden during reset configuration. See Table 30-6 for bit 
encodings.

7

RPLLSEL

PLL mode select. Reflects the default PLL mode.
0 1:1 PLL mode
1 Normal PLL mode (This is the value used for the MCF5282.)
The default PLL mode can be overridden during reset configuration. If the default is overridden, the 
clock module’s SYNSR[PLLSEL] bit reflects the PLL mode.