Motorola MVME2300 Series 用户手册
Programming Model
http://www.motorola.com/computer/literature
3-43
3
Scrub/Refresh Register
scb0,scb1
These bits increment every time the scrubber completes a
scrub of the entire DRAM. When these bits reach binary
11, they roll over to binary 00 and continue. They are
cleared by power-up reset.
scrub of the entire DRAM. When these bits reach binary
11, they roll over to binary 00 and continue. They are
cleared by power-up reset.
swen
When set, swen allows the scrubber to perform write
cycles. When cleared, swen prevents scrubber writes.
cycles. When cleared, swen prevents scrubber writes.
rtest0,1,2
The rtest bits enable certain refresh counter test modes.
modes are not intended to be used once the chip is in a
system.
system.
Address
$FEF80040
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
sc
b0
sc
b1
0
0
0
0
0
swe
n
0
0
0
0
0
rtest0
rtest1
rtest2
Operation
R
R
R
R
R
R
R
R/W
R
R
R
R
R
R/W
R/W
R/W
READ ZERO
READ ZERO
Reset
0 P
0 P
X
X
X
X
X
0 P
X
X
X
X
X
0 P
0 P
0 P
X
X
Table 3-13. rtest Encodings
rtest0,rtest1,rtest2
Test Mode selected
%000
Normal counter operation
%001
RA counts at 16x
%010
RA counts at 256x
%011
RA is always at roll value for CA
%100
CA counts at 16x
%101
CA counts at 256x
%110
Reserved
%111
Reserved