Motorola MVME2300 Series 用户手册
3-44
Computer Group Literature Center Web Site
Falcon ECC Memory Controller Chip Set
3
Refresh/Scrub Address Register
ROW ADDRESS
These bits form the row address counter used by the
refresher/scrubber for all blocks of DRAM. The row
address counter increments by one after each
refresh/scrub cycle. When it reaches all 1s, it rolls back
over to all 0s and continues counting. ROW ADDRESS is
readable and writable for test purposes.
refresher/scrubber for all blocks of DRAM. The row
address counter increments by one after each
refresh/scrub cycle. When it reaches all 1s, it rolls back
over to all 0s and continues counting. ROW ADDRESS is
readable and writable for test purposes.
Note that within each block, the most significant bits of
ROW ADDRESS are used only when their DRAM
devices are large enough to require them.
ROW ADDRESS are used only when their DRAM
devices are large enough to require them.
COL ADDRESS
These bits form the column address counter used by the
refresher/scrubber for all blocks of DRAM. The counter
increments by 1 every eighth time the ROW ADDRESS
rolls over. COL ADDRESS is readable and writable for
test purposes.
refresher/scrubber for all blocks of DRAM. The counter
increments by 1 every eighth time the ROW ADDRESS
rolls over. COL ADDRESS is readable and writable for
test purposes.
Note that within each block, the most significant bits of
COL ADDRESS are only used when their DRAM devices
are large enough to require them.
COL ADDRESS are only used when their DRAM devices
are large enough to require them.
Address
$FEF80048
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
0
0
0
ROW ADDRESS
0
0
0
COL ADDRESS
Operation
R
R
R
READ/WRITE
R
R
R
READ/WRITE
Reset
X
X
X
0 P
X
X
X
0 P