Motorola MVME2300 Series 用户手册
Functional Description
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the Universe. Write data is transferred to the PCI resource from the
RXFIFO without the involvement of the initiating VMEbus master (Refer
to Posted Writes in the Universe User Manual for a full explanation of this
operation.). With a coupled cycle, the VMEbus master only receives data
acknowledgment when the transaction is complete on the PCI bus. This
means that the VMEbus is unavailable to other masters while the PCI bus
transaction is executed.
RXFIFO without the involvement of the initiating VMEbus master (Refer
to Posted Writes in the Universe User Manual for a full explanation of this
operation.). With a coupled cycle, the VMEbus master only receives data
acknowledgment when the transaction is complete on the PCI bus. This
means that the VMEbus is unavailable to other masters while the PCI bus
transaction is executed.
Read transactions may be prefetched or coupled. If enabled by the user, a
prefetched read is initiated when a VMEbus master requests a block read
transaction (BLT or MBLT) and this mode is enabled. When the Universe
receives the block read request, it begins to fill its Read Data FIFO
(RDFIFO) using burst transactions from the PCI resource. The initiating
VMEbus master then acquires its block read data from the RDFIFO rather
than from the PCI resources directly.
prefetched read is initiated when a VMEbus master requests a block read
transaction (BLT or MBLT) and this mode is enabled. When the Universe
receives the block read request, it begins to fill its Read Data FIFO
(RDFIFO) using burst transactions from the PCI resource. The initiating
VMEbus master then acquires its block read data from the RDFIFO rather
than from the PCI resources directly.
Universe as VMEbus Master
The Universe becomes VMEbus master when the VME Master interface
is internally requested by the PCI Bus Slave channel, the DMA channel, or
the Interrupt channel. The Interrupt channel always has priority over the
other two channels. Several mechanisms are available to configure the
relative priority that the PCI Bus Slave channel and DMA channel have
over ownership of the VMEbus Master interface.
is internally requested by the PCI Bus Slave channel, the DMA channel, or
the Interrupt channel. The Interrupt channel always has priority over the
other two channels. Several mechanisms are available to configure the
relative priority that the PCI Bus Slave channel and DMA channel have
over ownership of the VMEbus Master interface.
The Universe’s VME Master interface generates all of the addressing and
data transfer modes documented in the VME64 specification (except A64
and those intended to support 3U applications, that is, A40 and MD32).
The Universe is also compatible with all VMEbus modules conforming to
pre-VME64 specifications. As VMEbus master, the Universe supports
Read-Modify-Write (RMW), and Address-Only-with-Handshake
(ADOH) but does not accept RETRY
data transfer modes documented in the VME64 specification (except A64
and those intended to support 3U applications, that is, A40 and MD32).
The Universe is also compatible with all VMEbus modules conforming to
pre-VME64 specifications. As VMEbus master, the Universe supports
Read-Modify-Write (RMW), and Address-Only-with-Handshake
(ADOH) but does not accept RETRY
∗
as a termination from the VMEbus
slave. The ADOH cycle is used to implement the VMEbus Lock
command, allowing a PCI master to lock VMEbus resources.
command, allowing a PCI master to lock VMEbus resources.
PCI Bus Interface
This section examines the Universe ASIC’s PCI bus interface function,
from the standpoint of the Universe as PCI slave as well as PCI master.
from the standpoint of the Universe as PCI slave as well as PCI master.