Motorola MVME2300 Series 用户手册
Functional Description
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4-7
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Interrupt sources mapped to PCI bus interrupts are generated on one of the
INT
INT
∗
[7:0] pins. To be fully PCI compliant, all interrupt sources must be
routed to a single INT
∗
pin.
For VMEbus interrupt outputs, the Universe interrupter supplies an 8-bit
STATUS/ID to a VMEbus interrupt handler during the IACK cycle, and
optionally generates an internal interrupt to signal that the interrupt vector
has been provided. (Refer to VMEbus Interrupt Generation in the Universe
User Manual.)
STATUS/ID to a VMEbus interrupt handler during the IACK cycle, and
optionally generates an internal interrupt to signal that the interrupt vector
has been provided. (Refer to VMEbus Interrupt Generation in the Universe
User Manual.)
Interrupts mapped to PCI bus outputs are serviced by the PCI interrupt
controller. The CPU determines which interrupt sources are active by
reading an interrupt status register in the Universe. The source negates its
interrupt when it has been serviced by the CPU. (Refer to PCI Interrupt
Generation in the Universe User Manual.)
controller. The CPU determines which interrupt sources are active by
reading an interrupt status register in the Universe. The source negates its
interrupt when it has been serviced by the CPU. (Refer to PCI Interrupt
Generation in the Universe User Manual.)
VMEbus Interrupt Handling
A VMEbus interrupt triggers the Universe to generate a normal VMEbus
IACK cycle and generate the specified interrupt output. When the IACK
cycle is complete, the Universe releases the VMEbus and the interrupt
vector is read by the PCI resource servicing the interrupt output. Software
interrupts are ROAK, while hardware and internal interrupts are RORA.
IACK cycle and generate the specified interrupt output. When the IACK
cycle is complete, the Universe releases the VMEbus and the interrupt
vector is read by the PCI resource servicing the interrupt output. Software
interrupts are ROAK, while hardware and internal interrupts are RORA.
DMA Controller
The Universe provides an internal DMA controller for high-performance
data transfer between the PCI bus and VMEbus. DMA operations between
the source and destination bus are decoupled through the use of a single
bidirectional FIFO (DMAFIFO). Parameters for the DMA transfer are
software configurable in the Universe registers. (Refer to DMA Controller
in the Universe User Manual.)
data transfer between the PCI bus and VMEbus. DMA operations between
the source and destination bus are decoupled through the use of a single
bidirectional FIFO (DMAFIFO). Parameters for the DMA transfer are
software configurable in the Universe registers. (Refer to DMA Controller
in the Universe User Manual.)
The principal mechanism for DMA transfers is the same for operations in
either direction (PCI to VME, or VME to PCI); only the relative identity
of the source and destination bus changes. In a DMA transfer, the Universe
gains control of the source bus and reads data into its DMAFIFO.
either direction (PCI to VME, or VME to PCI); only the relative identity
of the source and destination bus changes. In a DMA transfer, the Universe
gains control of the source bus and reads data into its DMAFIFO.