Motorola MVME2300 Series 用户手册
4-6
Computer Group Literature Center Web Site
Universe (VMEbus to PCI) Chip
4
Universe as PCI Slave
Read transactions from the PCI bus are always processed as coupled. Write
transactions may be either coupled or posted, depending upon the setting
of the PCI bus slave image. (Refer to PCI Bus Slave Images in the Universe
User Manual.) With a posted write transaction, write data is written to a
Posted Write Transmit FIFO (TXFIFO) and the PCI bus master receives
data acknowledgment from the Universe with zero wait states. Meanwhile,
the Universe obtains the VMEbus and writes the data to the VMEbus
resource independent of the initiating PCI master. (Refer to Posted Writes
in the Universe User Manual for a full description of this operation.)
transactions may be either coupled or posted, depending upon the setting
of the PCI bus slave image. (Refer to PCI Bus Slave Images in the Universe
User Manual.) With a posted write transaction, write data is written to a
Posted Write Transmit FIFO (TXFIFO) and the PCI bus master receives
data acknowledgment from the Universe with zero wait states. Meanwhile,
the Universe obtains the VMEbus and writes the data to the VMEbus
resource independent of the initiating PCI master. (Refer to Posted Writes
in the Universe User Manual for a full description of this operation.)
To allow PCI masters to perform RMW and ADOH cycles, the Universe
provides a Special Cycle Generator. The Special Cycle Generator can be
used in combination with a VMEbus ownership function to guarantee PCI
masters exclusive access to VMEbus resources over several VMEbus
transactions. (Refer to Exclusive Accesses and RMW and ADOH Cycles in
the Universe User Manual for a full description of this functionality.)
provides a Special Cycle Generator. The Special Cycle Generator can be
used in combination with a VMEbus ownership function to guarantee PCI
masters exclusive access to VMEbus resources over several VMEbus
transactions. (Refer to Exclusive Accesses and RMW and ADOH Cycles in
the Universe User Manual for a full description of this functionality.)
Universe as PCI Master
The Universe becomes PCI master when the PCI Master Interface is
internally requested by the VME Slave Channel or the DMA Channel.
There are mechanisms provided which allow the user to configure the
relative priority of the VME Slave Channel and the DMA Channel.
internally requested by the VME Slave Channel or the DMA Channel.
There are mechanisms provided which allow the user to configure the
relative priority of the VME Slave Channel and the DMA Channel.
Interrupter
The Universe interrupt channel provides a flexible scheme to map
interrupts to either the PCI bus or VMEbus interface. Interrupts are
generated from either hardware or software sources (refer to the
Interrupter section of the Universe User Manual for a full description of
hardware and software sources). Interrupt sources can be mapped to any of
the PCI bus or VMEbus interrupt output pins. Interrupt sources mapped to
VMEbus interrupts are generated on the VMEbus interrupt output pins
VIRQ
interrupts to either the PCI bus or VMEbus interface. Interrupts are
generated from either hardware or software sources (refer to the
Interrupter section of the Universe User Manual for a full description of
hardware and software sources). Interrupt sources can be mapped to any of
the PCI bus or VMEbus interrupt output pins. Interrupt sources mapped to
VMEbus interrupts are generated on the VMEbus interrupt output pins
VIRQ
∗
[7:1]. When a software and hardware source are assigned the same
VIRQn
∗
pin, the software source always has higher priority.