Motorola MVME172 用户手册
3-32
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MC2 Chip
3
LANC Bus Error Interrupt Control Register
IL2-IL0
Interrupt Request Level. These three bits select the
interrupt level for the 82596CA LANC bus error
condition. Level 0 does not generate an interrupt.
interrupt level for the 82596CA LANC bus error
condition. Level 0 does not generate an interrupt.
ICLR
Writing a logic 1 into this bit clears the INT status bit.
This bit is always read as zero.
This bit is always read as zero.
IEN
Interrupt Enable. When this bit set high, the interrupt is
enabled. The interrupt is disabled when this bit is low.
enabled. The interrupt is disabled when this bit is low.
INT
Interrupt Status. When this bit is high, a LANC Bus Error
interrupt is being generated at the level programmed in
IL2-IL0.
interrupt is being generated at the level programmed in
IL2-IL0.
SC0
Snoop Control.
0 Snoop enabled
1 Snoop disabled
1 Snoop disabled
ADR/SIZ
$FFF42028 (8 bits)
BIT
7
6
5
4
3
2
1
0
NAME
SC1
SC0
INT
IEN
ICLR
IL2
IL1
IL0
OPER
R/W
R/W
R
R/W
C
R/W
R/W
R/W
RESET
0 PL
0 PL
0 PL
0 PL
0
0 PL
0 PL
0 PL