Intel IXC1100 用户手册

Intel

®

 IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

September 2006

DM

Order Number: 252480-006US

299

Each chip select can be independently enabled or disabled by setting a value in bit 31 of 

each Timing and Control (EXP_TIMING_CS) Register. Setting bit 31 — of the Timing 

and Control (EXP_TIMING_CS) Register — to logic 0 disables the corresponding chip 

select. Setting bit 31 — of the Timing and Control (EXP_TIMING_CS) Register — to 

logic 1 enables the corresponding chip select.

Split transfers are supported for all transfer types and controlled by setting bit 3 of the 

Timing and Control (EXP_TIMING_CS) Register. Multi-word read transfers requested by 

the South AHB might be split. Only one access at a time may be split. 

These transfers require that the read data from the expansion bus be stored in an 

eight-word FIFO — until all expansion-bus transfers are complete — before that data is 

forwarded on the South AHB. When split transfers are initiated, the Expansion Bus 

Controller acknowledges the read request. The South AHB will be relinquished until all 

the data is acquired from the expansion bus and stored in the eight-word FIFO 

contained in the Expansion Bus Controller. 

After all of the data has been acquired by the Expansion Bus Controller, the requesting 

master on the South AHB will be signaled that the read data is in the FIFO and the read 

transfer will complete — uninterrupted in its normal rotation in the arbitration scheme. 

This feature allows for slow devices — connected to the expansion bus — not to impede 

the performance of data flow from high-speed peripherals (like PCI) on the South AHB. 

Retries also are supported and used predominately when expansion-bus requests are 

issued while a split transfer is in progress. Setting bit 3 — of each Timing and Control 

(EXP_TIMING_CS) Register — to logic 1 enables split transfers for accesses to the 

corresponding chip select. Setting bit 3 — of each Timing and Control 

(EXP_TIMING_CS) Register — to logic 0 disables split transfers for accesses to the 

corresponding chip select. 

For Chip Select 0, split transfers are disabled after reset. This feature allows the boot 

device to provide uninterrupted 32-bit data words to the Intel XScale processor.

Each chip select region has the ability to be write-protected by setting bit 1 of each 

Timing and Control (EXP_TIMING_CS) Register. When bit 1 of Timing and Control 

(EXP_TIMING_CS) Register is set to logic 0, writes to a specified chip select region are 

ignored. When bit 1 of Timing and Control (EXP_TIMING_CS) Register is set to logic 1, 

writes are allowed to a specified chip select region. Chip select 0 will be write-protected 

after reset.

For chip selects 4 through 7 configured in HPI mode of operation, there is an associated 

ready bit (EX_RDY [0:3]). The ready bit is only used when the mode of operation is set 

to Texas Instruments HPI mode. The ready bits are used to hold off the Intel XScale 

processor when the given DSP is not ready to complete the transfer. 

However, the polarity of this ready bit can vary based upon the DSP that is selected. Bit 

5 of each Timing and Control (EXP_TIMING_CS) Register allows the polarity used by 

each ready bit to be independently set. When bit 5 — of the Timing and Control 

(EXP_TIMING_CS) Register — is set to logic 0, the ready bit is set to respond to an 

active low signal (logic 0). When bit 5 — of the Timing and Control (EXP_TIMING_CS) 

Register — is set to logic 1, the ready bit is set to respond to an active high signal (logic 

1).

One final set of parameters that may be set prior to using Expansion Bus Interface Chip 

Select 1 through Chip Select 8. After boot up, these parameters may be adjusted for 

Chip Select 0 as well. These five parameters are the timing extension parameters for 

each phase of an Expansion Bus access.

There are five phases to every Expansion Bus access:

• T1 – Address Timing