SMSC LAN9311 用户手册
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
225
Revision 1.4 (08-19-08)
DATASHEET
13
Alternate MAC Address 1 Enable Port 0(Host MAC)
(MAC_ALT1_EN_MII)
This bit enables/disables the alternate MAC address 1 on Port 0.
(MAC_ALT1_EN_MII)
This bit enables/disables the alternate MAC address 1 on Port 0.
0: Disables alternate MAC address on Port 0
1: Enables MAC address 01:00:5E:00:01:82 as a PTP address on Port 0
1: Enables MAC address 01:00:5E:00:01:82 as a PTP address on Port 0
R/W
0b
12
Alternate MAC Address 2 Enable Port 0(Host MAC)
(MAC_ALT2_EN_MII)
This bit enables/disables the alternate MAC address 2 on Port 0.
(MAC_ALT2_EN_MII)
This bit enables/disables the alternate MAC address 2 on Port 0.
0: Disables alternate MAC address on Port 0
1: Enables MAC address 01:00:5E:00:01:83 as a PTP address on Port 0
1: Enables MAC address 01:00:5E:00:01:83 as a PTP address on Port 0
R/W
0b
11
Alternate MAC Address 3 Enable Port 0(Host MAC)
(MAC_ALT3_EN_MII)
This bit enables/disables the alternate MAC address 3 on Port 0.
(MAC_ALT3_EN_MII)
This bit enables/disables the alternate MAC address 3 on Port 0.
0: Disables alternate MAC address on Port 0
1: Enables MAC address 01:00:5E:00:01:84 as a PTP address on Port 0
1: Enables MAC address 01:00:5E:00:01:84 as a PTP address on Port 0
R/W
0b
10
User Defined MAC Address Enable Port 0(Host MAC)
(MAC_USER_EN_MII)
This bit enables/disables the auxiliary MAC address on Port 0. The auxiliary
address is defined via the 1588_AUX_MAC_HI and 1588_AUX_MAC_LO
registers.
(MAC_USER_EN_MII)
This bit enables/disables the auxiliary MAC address on Port 0. The auxiliary
address is defined via the 1588_AUX_MAC_HI and 1588_AUX_MAC_LO
registers.
0: Disables auxiliary MAC address on Port 0
1: Enables auxiliary MAC address as a PTP address on Port 0
1: Enables auxiliary MAC address as a PTP address on Port 0
R/W
0b
9
Lock Enable RX Port 0(Host MAC) (LOCK_RX_MII)
This bit enables/disables the RX lock. This lock prevents a 1588 capture
from overwriting the Clock, UUDI and Sequence ID values if the 1588 RX
interrupt for Port 0 is ready set due to a previous capture.
This bit enables/disables the RX lock. This lock prevents a 1588 capture
from overwriting the Clock, UUDI and Sequence ID values if the 1588 RX
interrupt for Port 0 is ready set due to a previous capture.
0: Disables RX Port 0 Lock
1: Enables RX Port 0 Lock
1: Enables RX Port 0 Lock
Note:
For Port 0, receive is defined as data from the switch fabric, while
transmit is to the switch fabric.
transmit is to the switch fabric.
R/W
1b
8
Lock Enable TX Port 0(Host MAC) (LOCK_TX_MII)
This bit enables/disables the TX lock. This lock prevents a 1588 capture
from overwriting the Clock, UUDI and Sequence ID values if the 1588 TX
interrupt for Port 0 is ready set due to a previous capture.
This bit enables/disables the TX lock. This lock prevents a 1588 capture
from overwriting the Clock, UUDI and Sequence ID values if the 1588 TX
interrupt for Port 0 is ready set due to a previous capture.
0: Disables TX Port 0 Lock
1: Enables TX Port 0 Lock
1: Enables TX Port 0 Lock
Note:
For Port 0, receive is defined as data from the switch fabric, while
transmit is to the switch fabric.
transmit is to the switch fabric.
R/W
1b
7
RESERVED
RO
-
6
Lock Enable GPIO 9 (LOCK_GPIO_9)
This bit enables/disables the GPIO 9 lock. This lock prevents a 1588 capture
from overwriting the Clock value if the 1588_GPIO9 interrupt in the
This bit enables/disables the GPIO 9 lock. This lock prevents a 1588 capture
from overwriting the Clock value if the 1588_GPIO9 interrupt in the
is already set
due to a previous capture.
0: Disables GPIO 9 Lock
1: Enables GPIO 9 Lock
1: Enables GPIO 9 Lock
R/W
1b
BITS
DESCRIPTION
TYPE
DEFAULT