SMSC LAN9311 用户手册

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

SMSC LAN9311/LAN9311i

227

Revision 1.4 (08-19-08)

 

This read/write register contains the IEEE 1588 interrupt status and enable bits. 

Writing a 1 to any of the interrupt status bits acknowledges and clears the interrupt. If enabled, these
interrupt bits are cascaded into bit 29 (1588_EVNT) of the 

. Writing

a 1 to any of the interrupt enable bits will enable the corresponding interrupt as a source. Status bits
will still reflect the status of the interrupt source regardless of whether the source is enabled as an
interrupt in this register. Bit 29 (1588_EVNT_EN) of the 

 must also

be set in order for an actual system level interrupt to occur. Refer to 

 for additional information.

Offset:

198h

Size:

32 bits

31:25

RO

-

24

R/W

0b

23

R/W

0b

22

R/W

0b

21

R/W

0b

20

R/W

0b

19

R/W

0b

18

R/W

0b

17

R/W

0b

16

R/W

0b

15:9

RO

-

8

1588 Port 2 RX Interrupt (1588_PORT2_RX_INT)
This interrupt indicates that a packet received by Port 2 matches the 
configured PTP packet and the 1588 clock was captured.

R/WC

0b

7

1588 Port 2 TX Interrupt (1588_PORT2_TX_INT)
This interrupt indicates that a packet transmitted by Port 2 matches the 
configured PTP packet and the 1588 clock was captured.

R/WC

0b

6

1588 Port 1 RX Interrupt (1588_PORT1_RX_INT)
This interrupt indicates that a packet received by Port 1 matches the 
configured PTP packet and the 1588 clock was captured.

R/WC

0b

5

1588 Port 1 TX Interrupt (1588_PORT1_TX_INT)
This interrupt indicates that a packet transmitted by Port 1 matches the 
configured PTP packet and the 1588 clock was captured.

R/WC

0b

4

1588 Port 0(Host MAC) RX Interrupt (1588_MII_RX_INT)
This interrupt indicates that a packet from the switch fabric to the Host MAC 
the matches the configured PTP packet and the 1588 clock was captured.

For Port 0, receive is defined as data from the switch fabric, while 
transmit is to the switch fabric.

R/WC

0b