High Power HPC-500-H12S 用户手册

 

 

 
 

 

 

A TTL compatible signal for the purpose of initiating an orderly start-up procedure under 

normal input operating conditions. During power up, this signal is asserted ( low ) until +5V is 

under regulation and AC reaches min. line specification range. After all voltage are going 

appropriate level, the system may have a turn on delay of 100mS, but no greater than 500mS. 

During power off the signal should go to low level before +5V is out of regulation. The low 

level is 0 to 0.8V and high level is 4.75 to 5.25V. The " Power Good "signal can drive up to 6 

standard TTL loads. 

 

Time Diagram                                                              

Figure 1

 

 

* T1 : Turn on time ( 2 sec. Max.)   

 

* T2 : Rise time ( ≦ 20mS Max.) 

* T3 : Power good turn on delay time ( 100 < T3 < 500 mS ) 

* T4 : Switch on time (0.5 sec. Max.) 

* T5 : Power good turn off delay time ( 1.0 mS Min.) PS-ON/OFF 

* T6 : Power hold-up time ( 8 mS Min.) 

* Power on-off cycle :  

When the power supply is turned off for a minimum of 2.0 sec. and turn on again, the power 

good signal will be asserted.