Freescale Semiconductor Tower System Development Board TWR-56F8400 TWR-56F8400 TWR-56F8400 信息指南

• Channels not used for PWM generation can be used for input capture functions
• Enhanced dual edge capture functionality

• Synchronization to external hardware or other PWM supported
• Double buffered PWM registers

• Integral reload rates from 1 to 16
• Half-cycle reload capability

• Multiple output trigger events can be generated per PWM cycle via hardware
• Support for double switching PWM outputs
• Up to eight fault inputs can be assigned to control multiple PWM outputs

• Programmable filters for fault inputs

• Independently programmable PWM output polarity
• Individual software control of each PWM output
• All outputs can be programmed to change simultaneously via a FORCE_OUT event
• PWMX pin can optionally output a third PWM signal from each submodule
• Option to supply the source for each complementary PWM signal pair from any of the following:

• Crossbar module outputs
• External ADC input, taking into account values set in ADC high and low limit registers

• Four 16-bit up/down counters with programmable prescaler for each counter
• Operation modes: edge count, gated count, signed count, capture, compare, PWM, signal shot, single pulse, pulse

string, cascaded, quadrature decode

• Programmable input filter
• Counting start can be synchronized across counters

• Includes logic to decode quadrature signals
• Configurable digital filter for inputs to remove glitches and ensure only true transitions are recorded
• 32-bit position counter register
• 16-bit position difference register
• Maximum count frequency equals the IPBus clock rate
• Position counter can be initialized by software or external events
• Position counter and resolution counter can be captured by external trigger signal (new feature)
• Preloadable 16-bit revolution counter
• Inputs can be connected to a general purpose timer, aiding low speed velocity measurements
• Watchdog timer to detect a non-rotating shaft condition
• Optional use as a single phase pulse accumulator

• 16-bit up-counter with programmable counter modulo
• Interrupt capability
• Selectable clock sources:

• External crystal oscillator/external clock source
• On-chip low-power 32 kHz oscillator
• System bus (IPBus up to 100 MHz)
• 8 MHz / 400 kHz ROSC

• Can signal the device to exit powerdown mode
• Programmable master/slave selection between PIT instances

• 16-bit counter with programmable counter modulo and delay time

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Freescale Semiconductor, Inc.