Freescale Semiconductor Tower System Development Board TWR-56F8400 TWR-56F8400 TWR-56F8400 信息指南
产品代码
TWR-56F8400
• Counter is initiated by positive transition of internal or external trigger pulse
• Support for synchronizing PWM and ADC conversions
• Two PDB outputs can be ORed together to schedule two conversions from one input trigger event
• PDB outputs can be used to schedule precise edge placement for a pulsed output that generates the control signal for
• Support for synchronizing PWM and ADC conversions
• Two PDB outputs can be ORed together to schedule two conversions from one input trigger event
• PDB outputs can be used to schedule precise edge placement for a pulsed output that generates the control signal for
the CMP windowing comparison
• Support for continuous mode or single shot mode
• Bypass mode supported
• Bypass mode supported
3.7.3.6 Computer Operating Properly (COP) Watchdog
• Programmable timeout period
• Support for operation in all power modes: run mode, wait mode, stop mode
• Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected
• Selectable reference clock source in support of EN60730 and IEC61508
• Selectable clock sources:
• Support for operation in all power modes: run mode, wait mode, stop mode
• Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected
• Selectable reference clock source in support of EN60730 and IEC61508
• Selectable clock sources:
• External crystal oscillator/external clock source
• On-chip low-power 32 kHz oscillator
• System bus (IPBus up to 100 MHz)
• 8 MHz / 400 kHz ROSC
• On-chip low-power 32 kHz oscillator
• System bus (IPBus up to 100 MHz)
• 8 MHz / 400 kHz ROSC
• Support for interrupt triggered when the counter reaches the timeout value
3.7.3.7 External Watchdog Monitor (EWM)
• Monitors external circuit as well as the software flow
• Programmable time-out period
• Interrupt capability prior to time-out
• Independent output (EWM_OUT_b) that places external circuit (but not CPU and peripheral) in a safe mode when
• Programmable time-out period
• Interrupt capability prior to time-out
• Independent output (EWM_OUT_b) that places external circuit (but not CPU and peripheral) in a safe mode when
EWM time-out occurs
• Selectable reference clock source in support of EN60730 and IEC61508
• Wait mode and stop mode operation is not supported
• Selectable clock sources:
• Wait mode and stop mode operation is not supported
• Selectable clock sources:
• External crystal oscillator/external clock source
• On-chip low-power 32 kHz oscillator
• System bus (IPBus up to 100 MHz)
• 8 MHz / 400 kHz ROSC
• On-chip low-power 32 kHz oscillator
• System bus (IPBus up to 100 MHz)
• 8 MHz / 400 kHz ROSC
Clock Modules
3.7.4.1 On-Chip Oscillators
• Tunable 8 MHz relaxation oscillator with 400 kHz at standby mode (divide-by-two output)
• 32 kHz low frequency clock as secondary clock source for COP, EWM, PIT
• 32 kHz low frequency clock as secondary clock source for COP, EWM, PIT
3.7.4.2 Crystal Oscillator
• Support for both high ESR crystal oscillator (greater than 100-ohm ESR) and ceramic resonator
• 4 MHz to 16 MHz operating frequency
• 4 MHz to 16 MHz operating frequency
3.7.4.3 Phase Locked Loop
• Wide programmable output frequency: 240 MHz to 400 MHz
• Input reference clock frequency: 8 MHz to 16 MHz
• Input reference clock frequency: 8 MHz to 16 MHz
3.7.4
Clock Modules
MC56F844x/5x/7x Product Brief, Rev. 2, 06/2012
Freescale Semiconductor, Inc.
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