Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 用户手册
产品代码
DEMO9S12XHY256
Serial Communication Interface (S12SCIV5)
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
481
In
the verification samples RT3 and RT5 determine that the first low detected was noise and
not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag
is not set because the noise occurred before the start bit was found.
is not set because the noise occurred before the start bit was found.
Figure 14-22. Start Bit Search Example 1
In
, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the
perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data
recovery is successful.
recovery is successful.
Figure 14-23. Start Bit Search Example 2
Reset RT Clock
RT
1
RT
1
RT
1
RT
1
RT
2
RT
3
RT
4
RT
5
RT
1
RT
1
RT
2
RT
3
RT
4
RT
7
RT
6
RT
5
R
T10
RT
9
RT
8
R
T14
R
T13
R
T12
R
T11
R
T15
R
T16
RT
1
RT
2
RT
3
Samples
RT Clock
RT Clock Count
Start Bit
RXD
1
1
0
1
1
1
1
0
0
0
0
0
LSB
0
0
Reset RT Clock
RT
1
RT
1
RT
1
RT
1
RT
1
RT
1
RT
2
RT
3
RT
4
RT
5
RT
6
RT
7
RT
8
R
T11
R
T10
RT
9
R
T14
R
T13
R
T12
RT
2
RT
1
R
T16
R
T15
RT
3
RT
4
RT
5
RT
6
RT
7
Samples
RT Clock
RT Clock Count
Actual Start Bit
RXD
1
1
1
1
1
1
0
0
0
0
LSB
0
0
Perceived Start Bit