Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 用户手册

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Freescale Semiconductor

In

, a large burst of noise is perceived as the beginning of a start bit, although the test sample

at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived
bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.

shows the effect of noise early in the start bit time. Although this noise does not affect proper

synchronization with the start bit time, it does set the noise flag.

Reset RT Clock

RT

1

RT

1

RT

1

RT

1

RT

2

RT

3

RT

4

RT

5

RT

6

RT

7

RT

8

RT

9

R

T10

R

T13

R

T12

R

T11

R

T16

R

T15

R

T14

RT

4

RT

3

RT

2

RT

1

RT

5

RT

6

RT

7

RT

8

RT

9

Samples

RT Clock

RT Clock Count

Actual Start Bit

RXD

1

0

1

1

1

0

0

0

0

LSB

0

Perceived Start Bit

Reset RT Clock

RT1

RT1

RT1

RT1

RT1

RT1

RT1

RT1

RT1

RT1

RT2

RT3

RT4

RT7

RT6

RT5

RT10

RT9

RT8

RT14

RT13

RT12

RT11

RT15

RT16

RT1

RT2

RT3

Samples

RT Clock

RT Clock Count

Perceived and Actual Start Bit

RXD

1

1

1

1

1

0

0

1

LSB

1

1

1

1