Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 用户手册

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483

shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample

after the reset is low but is not preceded by three high samples that would qualify as a falling edge.
Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may
set the framing error flag.

In

, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the

noise flag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are
ignored.

If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it
sets the framing error flag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE flag
because a break character has no stop bit. The FE flag is set at the same time that the RDRF flag is set.

Reset RT Clock

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

2

RT

3

RT

4

RT

7

RT

6

RT

5

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

Samples

RT Clock

RT Clock Count

Start Bit

RXD

1

1

1

1

1

0

1

0

LSB

1

1

1

1

1

0

0

0

0

0

0

0

0

No Start Bit Found

Reset RT Clock

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

1

RT

2

RT

3

RT

4

RT

7

RT

6

RT

5

R

T10

RT

9

RT

8

R

T14

R

T13

R

T12

R

T11

R

T15

R

T16

RT

1

RT

2

RT

3

Samples

RT Clock

RT Clock Count

Start Bit

RXD

1

1

1

1

1

0

0

0

LSB

1

1

1

1

0

1

1

0