Nxp Semiconductors OM11043 数据表

LPC1769_68_67_66_65_64_63

All information provided in this document is subject to legal disclaimers.

© NXP Semiconductors N.V. 2014. All rights reserved.

 

[1]

The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive 

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated 
maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

SS

 unless 

otherwise noted.

c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not 

guaranteed. The conditions for functional operation are specified in 

.

[2]

Maximum/minimum voltage above the maximum operating voltage (see 

) and below ground that can be applied for a short time 

(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.

[3]

See 

 for maximum operating voltage.

[4]

Including voltage on outputs in 3-state mode.

[5]

V

DD

 present or not present. Compliant with the I

2

C-bus standard. 5.5 V can be applied to this pin when V

DD

 is powered down.

[6]

The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined 
based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.

[7]

Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k

 series resistor.

V

DD(3V3)

supply voltage (3.3 V)

external rail

0.5

+4.6

V

V

DD(REG)(3V3)

regulator supply voltage (3.3 V)

0.5

+4.6

V

V

DDA

analog 3.3 V pad supply 
voltage

0.5

+4.6

V

V

i(VBAT)

input voltage on pin VBAT

for the RTC

0.5

+4.6

V

V

i(VREFP)

input voltage on pin VREFP

0.5

+4.6

V

V

IA

analog input voltage

on ADC related pins

0.5

+5.1

V

V

I

input voltage

5 V tolerant digital I/O pins; 
V

DD

 

 2.4 V

0.5

+5.5

V

I

V

DD

 = 0 V

0.5

+3.6

5 V tolerant open-drain pins 
PIO0_27 and PIO0_28

0.5

+5.5

I

DD

supply current

per supply pin

-

100

mA

I

SS

ground current

per ground pin

-

100

mA

I

latch

I/O latch-up current

(0.5V

DD(3V3)

) < V

I

 < 

(1.5V

DD(3V3)

); T

j

 < 125

C

-

100

mA

T

stg

storage temperature

65

+150

C

T

j(max)

maximum junction temperature

150

C

P

tot(pack)

total power dissipation (per 
package)

based on package heat 
transfer, not device power 
consumption

-

1.5

W

V

ESD

electrostatic discharge voltage

human body model; all pins

4000

+4000

V