Acorn Products Z80 SECOND PROCESSSOR 409 用户手册
signal to the CPU is a pulse of approx. 4µs duration, sufficient to
produce a reset without delaying the refresh to the DRAMS and so
losing data. The reset to the CPU also clears the ROM latch IC15A,
bringing the shadow ROM into the memory-map.
The Schmitt NAND gate IC19C provides a Power-Up reset to' the Z80 from
produce a reset without delaying the refresh to the DRAMS and so
losing data. The reset to the CPU also clears the ROM latch IC15A,
bringing the shadow ROM into the memory-map.
The Schmitt NAND gate IC19C provides a Power-Up reset to' the Z80 from
the delay network R1, C2 (time-constant 100ms). Diode D1 ensures that
the capacitor does not apply a reverse voltage to the NAND gate input
on Power-Down.
5.6 Interrupt Handling
The host processor can interrupt the Z80 with a maskable interrupt via
the Tube. The interrupt output from the Tube is taken directly to the
INT input of the Z80. After detection of an interrupt, the CPU M1 and
IORQ outputs go low to indicate a vector for the interrupt is expected
on the data bus D0 to D7. The buffer IC28 is enabled by M1 and IORQ
and its inputs are permanently tied to logic 0 or 1 to give a vector
address of 0FEH. The Z80 'Boot' ROM places the Z80 internal interrupt
system into Mode 2, with a High-Byte address of OFFH, giving an
address for the interrupt vector of 0FFFEH.
the Tube. The interrupt output from the Tube is taken directly to the
INT input of the Z80. After detection of an interrupt, the CPU M1 and
IORQ outputs go low to indicate a vector for the interrupt is expected
on the data bus D0 to D7. The buffer IC28 is enabled by M1 and IORQ
and its inputs are permanently tied to logic 0 or 1 to give a vector
address of 0FEH. The Z80 'Boot' ROM places the Z80 internal interrupt
system into Mode 2, with a High-Byte address of OFFH, giving an
address for the interrupt vector of 0FFFEH.
5.7 DRAM Control
5.7.1 Read/Write Cycles
a. RAS
Whenever a memory cycle occurs, the preset signal on the "D" latch
IC17B is removed by the MREQ signal from the Z80. On the next rising
edge of the system clock, the "D" latch output goes low, giving the "
CHOP" signal. During memory read or write cycles, the fa11ing edge of
CHOP produces the row-address (RAS) signal (TP8), via IC20A, to the
DRAMS, causing the row address information to be latched by the RAMS.
Prior to the RAS signal, the row-address buffer 1C5 was enabled by the
high level on RAS and consequently the low level on the inverted RAS
signal from 1C21A, thus allowing the low order address lines A0 to A7
to be passed to the DRAMS. Once RAS goes low, IC5 is disabled and IC4
enabled, to allow the column address through to the DRAMS. The
inverter IC25E ensures a slight delay in the enabling of the Column
buffer, to avoid data conflict with the Row buffer.
b. CAS
IC17B is removed by the MREQ signal from the Z80. On the next rising
edge of the system clock, the "D" latch output goes low, giving the "
CHOP" signal. During memory read or write cycles, the fa11ing edge of
CHOP produces the row-address (RAS) signal (TP8), via IC20A, to the
DRAMS, causing the row address information to be latched by the RAMS.
Prior to the RAS signal, the row-address buffer 1C5 was enabled by the
high level on RAS and consequently the low level on the inverted RAS
signal from 1C21A, thus allowing the low order address lines A0 to A7
to be passed to the DRAMS. Once RAS goes low, IC5 is disabled and IC4
enabled, to allow the column address through to the DRAMS. The
inverter IC25E ensures a slight delay in the enabling of the Column
buffer, to avoid data conflict with the Row buffer.
b. CAS
The column-address signal to the DRAMS is generated from the RAS
signal by the OR gates IC23C&D. If the shadow ROM output-enable signal
is active, then the CAS signal wi11 not be generated (logic 1 on pin
12 - IC23D). The AND gate 1C20C enables or disables the CAS signal
under certain other conditions.
signal by the OR gates IC23C&D. If the shadow ROM output-enable signal
is active, then the CAS signal wi11 not be generated (logic 1 on pin
12 - IC23D). The AND gate 1C20C enables or disables the CAS signal
under certain other conditions.