Intel 253668-032US User Manual
Vol. 3 2-33
SYSTEM ARCHITECTURE OVERVIEW
Fixed-function performance counters record only specific events that are defined in
Chapter 20, “Introduction to Virtual-Machine Extensions”, and the width/number of
fixed-function counters are enumerated by CPUID leaf 0AH.
The time-stamp counter is a model-specific 64-bit counter that is reset to zero each
time the processor is reset. If not reset, the counter will increment ~9.5 x 10
Chapter 20, “Introduction to Virtual-Machine Extensions”, and the width/number of
fixed-function counters are enumerated by CPUID leaf 0AH.
The time-stamp counter is a model-specific 64-bit counter that is reset to zero each
time the processor is reset. If not reset, the counter will increment ~9.5 x 10
16
times per year when the processor is operating at a clock rate of 3GHz. At this
clock frequency, it would take over 190 years for the counter to wrap around. The
RDTSC instruction loads the current count of the time-stamp counter into the
EDX:EAX registers.
See Section 30.1, “Performance Monitoring Overview,” and Section 16.11, “Time-
Stamp Counter,” for more information about the performance monitoring and time-
stamp counters.
The RDTSC instruction was introduced into the IA-32 architecture with the Pentium
processor. The RDPMC instruction was introduced into the IA-32 architecture with the
Pentium Pro processor and the Pentium processor with MMX technology. Earlier
Pentium processors have two performance-monitoring counters, but they can be
read only with the RDMSR instruction, and only at privilege level 0.
clock frequency, it would take over 190 years for the counter to wrap around. The
RDTSC instruction loads the current count of the time-stamp counter into the
EDX:EAX registers.
See Section 30.1, “Performance Monitoring Overview,” and Section 16.11, “Time-
Stamp Counter,” for more information about the performance monitoring and time-
stamp counters.
The RDTSC instruction was introduced into the IA-32 architecture with the Pentium
processor. The RDPMC instruction was introduced into the IA-32 architecture with the
Pentium Pro processor and the Pentium processor with MMX technology. Earlier
Pentium processors have two performance-monitoring counters, but they can be
read only with the RDMSR instruction, and only at privilege level 0.
2.7.6.1
Reading Counters in 64-Bit Mode
In 64-bit mode, RDTSC operates the same as in protected mode. The count in the
time-stamp counter is stored in EDX:EAX (or RDX[31:0]:RAX[31:0] with
RDX[63:32]:RAX[63:32] cleared).
RDPMC requires an index to specify the offset of the performance-monitoring
counter. In 64-bit mode for Pentium 4 or Intel Xeon processor families, the index is
specified in ECX[30:0]. The current count of the performance-monitoring counter is
stored in EDX:EAX (or RDX[31:0]:RAX[31:0] with RDX[63:32]:RAX[63:32]
cleared).
time-stamp counter is stored in EDX:EAX (or RDX[31:0]:RAX[31:0] with
RDX[63:32]:RAX[63:32] cleared).
RDPMC requires an index to specify the offset of the performance-monitoring
counter. In 64-bit mode for Pentium 4 or Intel Xeon processor families, the index is
specified in ECX[30:0]. The current count of the performance-monitoring counter is
stored in EDX:EAX (or RDX[31:0]:RAX[31:0] with RDX[63:32]:RAX[63:32]
cleared).
2.7.7
Reading and Writing Model-Specific Registers
The RDMSR (read model-specific register) and WRMSR (write model-specific
register) instructions allow a processor’s 64-bit model-specific registers (MSRs) to be
read and written, respectively. The MSR to be read or written is specified by the value
in the ECX register.
register) instructions allow a processor’s 64-bit model-specific registers (MSRs) to be
read and written, respectively. The MSR to be read or written is specified by the value
in the ECX register.
RDMSR reads the value from the specified MSR to the EDX:EAX registers; WRMSR
writes the value in the EDX:EAX registers to the specified MSR. RDMSR and WRMSR
were introduced into the IA-32 architecture with the Pentium processor.
See Section 9.4, “Model-Specific Registers (MSRs),” for more information.
writes the value in the EDX:EAX registers to the specified MSR. RDMSR and WRMSR
were introduced into the IA-32 architecture with the Pentium processor.
See Section 9.4, “Model-Specific Registers (MSRs),” for more information.