Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

1005

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The SMOD field in the AES_MR allows selection of the encryption (or decryption) start mode.

The sequence order is as follows:



Write the AES_MR with all required fields, including but not limited to SMOD and OPMOD.



Write the 128-bit/192-bit/256-bit key in the Key Registers (AES_KEYWRx).



Write the initialization vector (or counter) in the Initialization Vector Registers (AES_IVRx).

Note:

The Initialization Vector Registers concern all modes except ECB.



Set the bit DATRDY (Data Ready) in the AES Interrupt Enable register (AES_IER), depending on whether an 
interrupt is required or not at the end of processing.



Write the data to be encrypted/decrypted in the authorized Input Data Registers (See 

).

Note:

In 64-bit CFB mode, writing to AES_IDATAR2 and AES_IDATAR3 registers is not allowed and may lead to 
errors in processing.

Note:

In 32-, 16- and 8-bit CFB modes, writing to AES_IDATAR1, AES_IDATAR2 and AES_IDATAR3 registers is not 
allowed and may lead to errors in processing.



Set the START bit in the AES Control register AES_CR to begin the encryption or the decryption process.



When processing completes, the DATRDY bit in the AES Interrupt Status Register (AES_ISR) raises. If an 
interrupt has been enabled by setting the DATRDY bit in AES_IER, the interrupt line of the AES is activated.



When the software reads one of the Output Data Registers (AES_ODATARx), the DATRDY bit is automatically 
cleared.

The Auto Mode is similar to the manual one, except that in this mode, as soon as the correct number of Input Data
registers is written, processing is automatically started without any action in the Control Register.

The DMA Controller can be used in association with the AES to perform an encryption/decryption of a buffer without any
action by the software during processing.

The SMOD field of the AES_MR must be set to 0x2 and the DMA must be configured with non incremental addresses.

The start address of any transfer descriptor must be set to AES_IDATAR0.

The DMA chunk size configuration depends on the AES mode of operation and is listed in 

.

ECB

All

CBC

All

OFB

All

128-bit CFB 

All

 64-bit CFB

AES_IDATAR0 and AES_IDATAR1

 32-bit CFB

AES_IDATAR0

 16-bit CFB

AES_IDATAR0

 8-bit CFB

AES_IDATAR0

CTR

All