Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
1006
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
When writing data to AES with a first DMA channel, data are first fetched from a memory buffer (source data). It is
recommended to configure the size of source data to “words” even for CFB modes. On the contrary, the destination data
size depends on the mode of operation. When reading data from the AES with the second DMA channel, the source data
is the data read from AES and data destination is the memory buffer. In this case, source data size depends on the AES
mode of operation and is listed in
recommended to configure the size of source data to “words” even for CFB modes. On the contrary, the destination data
size depends on the mode of operation. When reading data from the AES with the second DMA channel, the source data
is the data read from AES and data destination is the memory buffer. In this case, source data size depends on the AES
mode of operation and is listed in
.
45.4.4 Last Output Data Mode
This mode is used to generate cryptographic checksums on data (MAC) by means of cipher block chaining encryption
algorithm (CBC-MAC algorithm for example).
algorithm (CBC-MAC algorithm for example).
After each end of encryption/decryption, the output data are available either on the output data registers for Manual and
Auto mode or at the address specified in the receive buffer pointer for DMA mode (See
Auto mode or at the address specified in the receive buffer pointer for DMA mode (See
The Last Output Data bit (LOD) in the AES Mode Register (AES_MR) allows retrieval of only the last data of several
encryption/decryption processes.
encryption/decryption processes.
Therefore, there is no need to define a read buffer in DMA mode.
This data are only available on the Output Data Registers (AES_ODATARx).
45.4.4.1 Manual and Auto Modes
If LOD = 0
The DATRDY flag is cleared when at least one of the Output Data Registers is read (See
Figure 45-1. Manual and Auto Modes with LOD = 0
If the user does not want to read the output data registers between each encryption/decryption, the DATRDY flag will not
be cleared. If the DATRDY flag is not cleared, the user cannot know the end of the following encryptions/decryptions.
be cleared. If the DATRDY flag is not cleared, the user cannot know the end of the following encryptions/decryptions.
Table 45-3. DMA Data Transfer Type for the Different Operation Modes
Operation Mode
Chunk Size
Destination/Source Data Transfer Type
ECB
4
Word
CBC
4
Word
OFB
4
Word
CFB 128-bit
4
Word
CFB 64-bit
1
Word
CFB 32-bit
1
Word
CFB 16-bit
1
Half-word
CFB 8-bit
1
Byte
CTR
4
Word
Encryption or Decryption Process
Read the AES_ODATARx
Write START bit in AES_CR (Manual mode)
DATRDY
Write AES_IDATARx register(s) (Auto mode)
or