Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
1007
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
If LOD = 1
The DATRDY flag is cleared when at least one Input Data Register is written, so before the start of a new transfer (See
Figure 45-2. Manual and Auto Modes with LOD = 1
45.4.4.2 DMA Mode
If LOD = 0
This mode may be used for all AES operating modes except CBC-MAC where LOD = 1 mode is recommended.
The end of the encryption/decryption is notified by the end of DMA transfer associated to AES_ODATARx (see
). Two DMA channels are required: one for writing message blocks to AES_IDATARx and one to obtain the result
from AES_ODATARx.
Figure 45-3. DMA transfer with LOD = 0
If LOD = 1
This mode is recommended to process AES CBC-MAC operating mode.
The user must first wait for the DMA flag (BTC = Buffer Transfer Complete) to rise, then for DATRDY to ensure that the
encryption/decryption is completed (see
encryption/decryption is completed (see
).
In this case, no receive buffers are required.
The output data are only available on the Output Data Registers (AES_ODATARx).
Write AES_IDATARx register(s)
Write START bit in AES_CR (Manual mode)
Write AES_IDATARx register(s) (Auto mode)
or
Encryption or Decryption Process
DATRDY
Enable DMA Channels associated to AES_IDATARx and AES_ODATARx
Multiple Encryption or Decryption Processes
BTC /channel 1
BTC /channel 0
Message fully processed
(cipher or decipher) last
block can be read
(cipher or decipher) last
block can be read
Write accesses into AES_IDATARx
Read accesses into AES_ODATARx