Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The Secure Hash Algorithm (SHA) is compliant with the American FIPS (Federal Information Processing Standard)
Publication 180-2 specification.

The 512-bit block of message is respectively stored in 16 x 32-bit registers (SHA_IDATARx/SHA_ODATARx) which are
all write-only.

As soon as the input data is written, the hash processing may be started. The registers comprising the block of a padded
message must be entered consecutively. Then the message digest is ready to be read out on the 5 up to 8 x 32-bit output
data registers (SHA_ODATARx) or through the DMA  channels.



Supports Secure Hash Algorithm (SHA1, SHA224, SHA256, ) 



Compliant with FIPS Publication 180-2



Configurable Processing Period: 



85 Clock Cycles to get a fast SHA1 runtime or 209  Clock Cycles for Maximizing Bandwidth of Other 
Applications



72 Clock Cycles to get a fast SHA224, SHA256 runtime or 194  Clock Cycles for Maximizing Bandwidth of 
Other Applications



Connection to DMA  Channel Capabilities Optimizes Data Transfers



Double Input Buffer Optimizes Runtime

The SHA may be clocked through the Power Management Controller (PMC), so the programmer must first configure the
PMC to enable the SHA clock.

The SHA interface has an interrupt line connected to the Interrupt Controller. 

Handling the SHA interrupt requires programming the interrupt controller before configuring the SHA.

SHA

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